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Tera-Pixel APS for CALICE

Tera-Pixel APS for CALICE. Progress 13 th November 2006. PreRst. Rst. Vrst. Vth+ Vth-. Rfb. Cpre. --ns. Cfb. RstSample. Rst. Cpre. Cstore. Buffer s.f. Buffer s.f. Vth+ Vth-. Cin. Preamp. Rin. Cin. Preamp. Shaper. --ns. PreSample Pixel. PreShape Pixel. New.

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Tera-Pixel APS for CALICE

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  1. Tera-Pixel APS for CALICE Progress 13th November 2006

  2. PreRst Rst Vrst Vth+ Vth- Rfb Cpre --ns Cfb RstSample Rst Cpre Cstore Buffer s.f Buffer s.f Vth+ Vth- Cin Preamp Rin Cin Preamp Shaper --ns PreSample Pixel PreShape Pixel New

  3. PreSample Pixel PreShape Pixel 11.8μW 7.7μW New 9.3μW

  4. 400 electron hit 60mV typ. 150uV/electron (~flat up to 10,000e- Reduces 50% by 20,000e) PreSample Pixel PreShape Pixel New 400 electron hit 120mV typ. requires reset (~600ns) 300uV/electron (30,000 electrons as 8 hits simulated ok) Un-reset shaped hit Reset

  5. Transient Noise 3.5mV typ at input to comparator ~ 25 electrons PreSample Pixel PreShape Pixel New Transient Noise 5.9mV typ at input to comparator *√2 = 8.3mV (*√2 due to sampling) ~ 27 electrons (was 32)

  6. Signal/Noise optimisation Larger diode capacitance increases noise PreSample Pixel PreShape Pixel New Signal/Noise optimisation Larger diode capacitance decreases signal (and therefore noise at input as equivalent charge)

  7. PreSample Pixel PreShape Pixel NWELL = 3 x 4 μm Add 5x9μm for pmos comparator sub-circuit New NWELL = 1.3 x 6.3 μm

  8. Disadvantages Preamp integrates charge (no reset) 20,000 electrons practical max Time-over-threshold up to 1us :  Needs edge-mode logic  Pixel is ‘dead’ during this time Advantages Always active (no reset) Shaper recovers after saturation Below-threshold signals do not integrate on the shaper. PreSample Pixel PreShape Pixel >10 MIP behaviour Saturation causes pulse elongation (dead time) Risks Cpre feedback cap New Advantages Flexible reset timing Pixel saturation occurs >30,000e- Disadvantages Below threshold signals are still integrated by the preamplifier Requires reset after hit  additional logic  dead time after hit Reset sample can contain error >10 MIP behaviour Signals over 4000e- may be a problem (needs investigation) Risks Cpre feedback cap

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