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Embedded System for Face Recognition

Xiaoguang(Shaw) LI Dr. Shawki Areibi Engineering System&Computing University of Guelph. Embedded System for Face Recognition. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16. Introduction Face images Input encoding Output encoding Network graph structure Implementation

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Embedded System for Face Recognition

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  1. Xiaoguang(Shaw) LI Dr. Shawki Areibi Engineering System&Computing University of Guelph Embedded System for Face Recognition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  2. Introduction Face images Input encoding Output encoding Network graph structure Implementation Architecture and BP pseudo code FSL with MicroBlaze Hardware “update” of BP Multimedia board Results and discussion Outline 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  3. Face Images Professor Tom M. Mitchell’s Machine Learning course 20 people each has 32 images Expression (happy,sad,angry,neutral) Direction(left,right,straight ahead,up) Eyes(open,close) Resolution(120*128) Grayscale intensity value(0(black),255(white)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  4. Input Encoding Features Intensity values 20 pixels rescale Intensity value of pixel 20 pixels 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  5. Output Encoding 4 images are tested Input and hidden output (1, 0, 0, 0) 1st person (0, 1, 0, 0) 2nd person (0, 0, 1, 0) 3rd person (0, 0, 0, 1) 4th person 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  6. Network graph structure 400 8 4 c[i](d(i)) w[i][j] a[i] b[i](e(i)) v[i][j] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  7. Pseudo code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  8. Architecture 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  9. FSL with MicroBlaze 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  10. FSL with MicroBlaze cont. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  11. Hardware “update” Inputs: Ready_cal (counter1) Ready_out (UPDATE UNIT) Done_out (counter2) 0XX Waiting 00 1XX XX1 Calculating Sending results 10 X1X 01 X0X XX0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  12. Hardware “update” cont. v[i][j]=v[i][j]+alpha*a[i]*e[j] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  13. Hardware “update” v[i][j]=v[i][j]+alpha*a[i]*e[j] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  14. Multimedia board • Xilinx Virtex2 2V2000 • Five independent banks of 512K x 36bit 130MHz ZBT RAM • 16M Flash 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  15. Results Works fine with 4 images 10 times faster just for “update” 30% faster for whole BP algorithm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  16. Discussion 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

  17. Questions?

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