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Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony

Technion - Israel institute of technology department of Electrical Engineering. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. High speed digital systems laboratory. המעבדה למערכות ספרתיות מהירות. דו”ח סיכום פרויקט Subject:. AMC – Adaptive Mirror Controller.

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Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony

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  1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט Subject: AMC – Adaptive Mirror Controller Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony Cooperated with: Physics Adaptive Optics Lab 2006-2007 1

  2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract The project is a collaboration between the Physics Adaptive Optics Lab and HS DSL. Developing a system that controls adaptive mirrors, by changing the voltage of their capacitors (up to 124 capacitors). The system will eventually be integrated into an optical device that present the image of the retina (the back of the eye). During this process the device will also fix the distortion of the picture that reflected by the cornea. 2

  3. AMC MMC USB USB Interface 8 Bit FPGA 12 Bit D/A Amp. Amp. Amp. Amp. Adaptive Mirror High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description 3

  4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • FPGA – Altera Cyclone EP1C3T144C8 • USB module - DLP-USB245M • D/A – Analog Devices quad voltage output AD5334 • High Voltage amplifiers – Supertex HV257 • Software • C++ driver based on the DLP-USB API 4

  5. HVAmp Power Supply Power Up/Down Unit Switches HVAmp Transceiver Transceiver Latch Bus Exchange Relay HVAmp Computer DLP (USB) Cyclone FPGA Transceiver Adaptive Mirror HVAmp Quad Voltage Output D/A Comparator CLK EPCS Reset HVAmp '1' High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram 5

  6. Power on AMC + USB cable connection! DLP, FPGA Power Up DLP ready! System Power Down HVAmp Power Up Power off AMC + USB cable disconnection! HVAmps are powered on HVAmp Power Down Self test Self Test Byte! MAIN OK/Error Massage Shutdown Byte! Status Byte! DLP to PC Transmit EOT = End Of Transmission WDTR = Watch Dog Timer Reset DLP = USB Module HVAmp = High Voltage Amplifier The Control Bytes are marks in green RUN Byte! EOT RUN All capacitors were charged/ WDTR! High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram Asinc to Sinc ROM State Machine 6

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