On Legalization of Row-Based Placements

1. On Legalization of Row-Based Placements Andrew B. Kahng Igor L. Markov Sherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093 abk@cs.ucsd.edu EECS Department University of Michigan Ann Arbor, MI 48109 imarkov@eecs.umich.edu CSE Department University of CA, San Diego La Jolla, CA 92093 sreda@cs.ucsd.edu VLSI CAD Laboratory at UCSD

2. Outline • Introduction and Previous Work • Legalization Objectives • Legalization Method • Experimental Results • Conclusions

3. Introduction: Objectives Used in Legalization An Illegal Placement due to Overlaps row Overlap cell • Overlap may be due: buffer insertion, gate sizing, etc • Overlap must be removed, sample objectives include minimizing: • Total distance moved, i.e., total perturbations • Total increase in HPWL (wirelength) • The maximum distance moved by a cell

4. Comparisons to Previous Work • Overlap removal algos in well-known VLSI placers (separate from detail placement optimization) • Simulated annealing in TimberWolf and Dragon • Greedy cell-shifting in Capo • Network flow in GORDIAN andBonnPlace • Dynamic programming in FengShui • Additional work • Whitespace allocation via dynamic programming by Kahng, Tucker and Zelikovsky • This Work • Develop a generic dynamic-programming algorithm that optimizes one of several objectives • Study the effect of the objective choice on total wirelength and routability

5. Outline • Introduction and previous work • Legalization Objectives • Legalization Method • Experimental Results • Conclusions

6. Overview of the Legalization Procedure We propose a two-phase approach for overlap removal: • Phase I: Juggle cells to meet row capacity constraints. • Phase II: Remove the overlaps within each row using a generic dynamic-programming approach according to a number of objectives.

7. Phase I: Cell Juggling Under-capacity rows Over-capacity rows • Juggle cells to meet row capacity constraints by moving cells from over-capacity rows to under-capacity rows.

8. Phase I: Cell Juggling Algorithm • Sort the rows in a non-increasing order according to over capacity • For each over-capacity row ro in order: 3. Repeat until row rois under capacity: 4. For each cell c in the row ro : find an under-capacity row ru such that moving c to ru yields the smallest increase in HPWL (wirelength) 5. Move the cell that yields the smallest increase in HPWL in Step 3.

9. Phase II: Overlap Removal Within Rows Overlap Overlap • Phase I outcome is a placement where the set of cells in every row meets the row capacity, but with possible overlaps. • A generic dynamic-programming technique removes all overlap while minimizing a number of objectives

10. Overlap Removal Using Dynamic Programming row start node sites 1 2 3 4 5 6 7 8 9 10 11 12 cell 1 cell 2 cell 3 cell n end node • Each chain represents the possible sites that a cell can be placed at • The order of chains correspond to the order of cells from left to right in a row

11. Overlap Removal Using Dynamic Programming row 1 2 sites 1 2 3 4 5 6 7 8 9 10 11 12 cell 1 cell 2 cell 3 cell n Start and end sites There are many paths from the start and end nodes → select the one that optimizes one of our objectives Sites that cell will be placed at Empty sites Sites not included in calculation

12. Min Total Distance Overlap Removal row c 2 1 0 1 2 3 4 5 6 7 8 9 2 1 0 1 2 3 4 5 6 7 8 • Label a diagonal edge starting at some column j and chain c by the difference in distance between j and current location of cell c. • 2. Label all horizontal edges by cost 0 • 3. Find the shortest path from start to end nodes using lexicographical sorting.

13. Min HPWL Overlap Removal Bounding box of a net connected to c row c 3 2 1 0 0 0 0 0 0 0 1 2 3 2 1 0 0 0 0 0 0 0 1 • Label a diagonal edge starting at some column j and chain c by the difference in HPWL between placing cell c at j and its current location • 2. Label all horizontal edges by cost 0 • 3. Find the shortest path from start to end nodes using lexicographical sorting. • This objective can be iterated (iterated minHPWL) a number of times until the percentage improvement in HPWL drops below 1% • Min HPWL has similarities to “Optimization of Linear Placements for Wirelength with Free sites,” Kahng, Tucker and Zelikovsky, ASPDAC’99.

14. Min-Max Displacement Overlap Removal row c 2 1 0 1 2 3 4 5 6 7 8 9 2 1 0 1 2 3 4 5 6 7 8 • Label a diagonal edge starting at some column j and chain c by the difference in distance between j and current location of cell c. • 2. Label all horizontal edges by cost 0 • 3. Find the path from start to end nodes that minimizes the maximum edge using lexicographical sort .

15. Outline • Introduction and Previous Work • Legalization Objectives • Legalization Method • Experimental Results • Conclusions

16. Experimental Results (IBM01) • We execute Capo (without its built-in legalizer) + Legalizer • Improvement percentage is relative to QPlace -eco

17. Experimental Results (IBM02) Flow: Capo → illegal placement → Legalizer • Improvement percentage is relative to QPlace -eco • Similar results are attained for remaining IBM benchmarks

18. Experimental Results Flow: Capo → illegal placement → Legalizer → Cadence’s WarpRoute • The min dist and min-max dist objectives attempt to preserve the whitespace map → preserves routability • Min HPWL objective optimizes wirelength, but may alter the whitespace map

19. Conclusions • The effect of cut directions on the amount of overlap is studied • A two-phase legalizer is proposed • A generic dynamic-programming that handles a number of legalization objectives: • Minimum-total displacement • Minimum-total HPWL • Minimum-Max displacement • The effect of various objectives on routability and wirelength are evaluated

20. Thanks

21. Introduction: Source of Overlaps in Min-cut Placement • Min-cut placement recursively partitions a circuit’s netlist and places the partitioned netlist in partitioned placement areas Figure I Figure II Figure III A vertical cut on a single row can be adjusted to fit the partition size A horizontal cut cannot be adjusted to fit the partition size → overlap may occur A vertical cut on a number of subrows creates twice the number of subrows → future overlaps when horizontal cuts are executed on them • If a partition has more total cell weight that its capacity → overlap occurs 1 2 Overlap

22. Effect of Cut-Sequence on Amount of Overlaps Relationship between number of vertical cuts, total Wirelength, and number of overlaps. • Vertical cuts on a number of rows are the main reason for overlaps in min-cut placement