COMMUNICATION BETWEEN ADSP-TS201 MULTIPROCESSOR SYSTEM

1. COMMUNICATION BETWEEN ADSP-TS201 MULTIPROCESSOR SYSTEM

2. INDEX • Why link port communication? • Block diagram and description • Link port architecture • Link port control registers • DMA channel control • Link transmission through DMA • Function used in C programming for optimization

3. WHY LINK PORT COMMUNICATION? • The processors access resources such as memory and peripherals by bus mastership process. • It’s time consuming process,processors have to wait for bus mastership even when they are not accessing common resources. • Requirement in the project is time critical.So in this project ,processor to processor communication via TigerSHARC link ports.

4. COMMANDS and DATA DSP PROCESSOR A COMMUNICATION CONTROLLER (TS201) DSP PROCESSOR B DATA CALCULATOR (TS201) LINK PORT 0 COMMANDS and DATA COMMAND COMMAND LINK PORT 2 LINK PORT 2 DATA DATA DSP PROCESSOR C DATA GENERATOR (TS201) DSP PROCESSOR D DATA GENERATOR (TS201) Block diagram and Description

5. COMMUNICATION CONTROLLER (DSP A) • Controls the flow of information receive from outside word • It transfer the information about application comes from UART like protocol to DSP B • Accept command from DSP B and DSP C over link port and exchange data to DSP B and DSP C as and when required.

6. DATA CALCULATOR(DSP B) • Functional master • Receives command from DSP C via DSP A and DSP D • Analyzed command and send data to respective DSPs. • Communication between DSP A and DSP B over link port 0 • DSP B and DSP D communicates using link port 2.

7. DATA GENRATOR(DSP C AND DSP D) • Two processors use for data generation • When they are ready to accept data send command to respective DSPs over link port 2. • It accept data from DSP A and DSP B using link port 2 DMA.

8. LINK PORT ARCHITECTURE

9. Each link port has two independent channels that can operate simultaneously. The transmit channel transfers data to a second device, and the receive channel gets data from second device.

10. Configuration of two ADSP-TS 201 processor

11. Link port control registers • The ADSP TS-201 processor’s link control register is splits into two control registers • Receive link control register(LRCTLx) • Transmit control register (LTCTLx) • These register define the flavor of the link protocol that is used in specific application. These registers are not to be changed during link operation. • Writing to a control register an active value is allowed only when the register has an inactive value.

12. Receive link control register

13. Transmit control register(LTCTLx)

14. DMA channel control • Transfer Control Block register (TCB) Each TCB divided into 4 32-bit register as follows • DMA index (DI) register • DMA X dimension count and increment (DX) register • DMA Y dimension count and increment (DY) register • DMA control and chaining pointer (DP) register

15. DMA block diagram

16. In the case of a transmitter TCB, the four words contain the address of the source data (DI), the number of words to be transferred (DX/DY), the address increment (DX/DY), and the control bits (DP). • In the case of a receiver TCB these four words contain destination address (DI), the number of words to be received (DX/DY), the address increment(DX/DY), and the control bits (DP).

17. DP register

19. DMA channel and Associated TCB registers

21. Link port transmission through DMA • Each link port associated with two DMA channel • The link port issues a service request to the transmit DMA channel when the LBUFTXx register is empty and the DMA channel is enabled. • The link port issues a DMA request to the receive link DMA channel when it receives a data quad-word—that is, when the LBUFRXx register is full and the DMA channel is enabled.

22. Function used in C programming for optimization • The builtins.h header file provides user-visible prototypes for the built-in functions. __builtin function used in program: • __builtin_sysreg_quad_write/read(name of registers) • __builtin_sysreg_quad_write4(name of registers )

23. __builtin_compose_128(long long, long long ) • The 128 bit TCB of DMA must be compose before load in respective register for transmission or reception by using function ‘__builtin_quad_compose_128(long long, long long)’ • This function used to compact or merge values to create larger or smaller types.

24. C CODE FOR LOAD THE DMA TCB e.g. The following code extract combines four long long variables’ data into a quad word of type __builtin_quad di=&Data; /*load index register (DI) of TCB of DMA*/ dx=0XC<<16 | MODIFY; /*load X count register (DX) of TCB of DMA*/ dy=0; /*load Y count register (DY) of TCB of DMA*/ dp=TCB_INTMEM | TCB_QUAD |TCB_INT ; /*load control and chaining pointer register (DP) of TCB of DMA*/

25. DC_SOURCE_TCB=__builtin_compose_128( (long, long) dx << 32 | di, (long long) dp << 32 | dy ); /*compose all four register of DMA TCB using command __builtin_compose_128*/ __builtin_sysreg_write4(__DC4, DC_SOURCE_TCB ); /*Load the TCB in register DC4 for transmission through link port 2 using command __builtin_sysreg_write4 */

26. __builtin_low/high_32() function to extract value: e.g. Program for extract the 32 bit command from 128 bit link port 0 receiver Buffer (LBUFRX0): x1 = __builtin_sysreg_read4(__LBUFRX0) ; /*read the 128 bit data receive in link port receiver buffer */ tempvar1= __builtin_low_64(x1); /*Extract lower 64 bit from 128-bit */ tempvar2 =__builtin_low_32(tempvar1); /*extract lower 32 bit from 64bit*/

27. Examples • /*Configure LP0 in Rx mode to receive command from TTG*/ XR0 =0x0;; lrctl0 = xr0;; xr0 = LRCTL_REN |LRCTL_RDSIZE;; lrctl0 = xr0;;

28. Program for transmit the command XR3 = 0x0;; XR2 = 0x0;; XR1 = 0x0;; XR0 = 0x00005555 ;; LBUFTX2= XR3:0 ;; /* enable link port 2 to transmit get status command*/ xr0=LTCTL_TEN |LTCTL_TDSIZE | LTCTL_TCLKDIV4 ;

29. Program for load DMA .section data1; .var Parameters[12]; .VAR DC4_SOURCE_TCB[4]= Parameters, /*LOAD DI REGISTER*/ 0XC<<16 | modify, /*LOAD DX REGISTER*/ 0x0, /*LOAD DY REGISTER*/ TCB_INTMEM | TCB_QUAD |TCB_INT ; /*LOAD DP REGISTER*/ /*Configure link port 0 Tx DMA TCB to transmit Info to TTG*/ J0= j31 + DC4_SOURCE_TCB;; XR3:0= Q[J0 + J31];; DC4 = XR3:0;;

30. THANK YOU

31. QURRIES AND QUESTIONS?