1 / 8

CDA 3100

CDA 3100. Recitation Week 11. Design a 2-bit counter:. Count in the order of 0, 3, 1, 2, 0, 3, 1, 2, … Use a D flip-flop Construct your truth table in the form of a next state diagram That is if input is 00, output is 11. Design 4-bit encoder: Truth ( Next State) Table.

casta
Download Presentation

CDA 3100

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CDA 3100 Recitation Week 11

  2. Design a 2-bit counter: • Count in the order of 0, 3, 1, 2, 0, 3, 1, 2, … • Use a D flip-flop • Construct your truth table in the form of a next state diagram • That is if input is 00, output is 11

  3. Design 4-bit encoder: Truth (Next State)Table

  4. Design 4-bit encoder:K-Map for D1 Q1 Q0 D1 = ~Q1

  5. Design 4-bit encoder:K-Map for D0 Q1 Q0 D0 = (~Q1 * ~Q0) + (Q1 * Q0) = ~(Q1 xor Q0)

  6. Verilog Code: • Write a Verilog module to have the same effect as the 2-bit counter implemented earlier • Just a reminder • D1 = ~Q1 • D0 = ~(Q1 ^ Q0) • You don’t have to reimplement the D flip-flop module, just use the one presented in class • module Dff1(D, clk, Q, Qbar); • Your module’s prototype will look like: • module counter_2_bit(clk, Q);

  7. Verilog Code:Dff1 Module Dff1 (D, clk, Q, Qbar); input D, clk; output reg Q, Qbar; initial begin Q = 0; Qbar = 1; end always @(posedgeclk) begin #1 Q = D; #1 Qbar = ~Q; end endmodule

  8. Verilog Code:counter_2_bit module counter_2_bit(clk, Q); input clk; output [1:0] Q; wire Q1, Q1bar, Q0, Q0bar, D1, D0; assign D0 = ~(Q1 ^ Q0); Dff1 C0(D0, clk, Q0, Q0bar); assign D1 = ~Q1; Dff1 C1(D1, clk, Q1, Q1bar); assign Q[1] = Q1; assign Q[0] = Q0; endmodule

More Related