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Lecture X

Lecture X. Algorithmic State Machines. State Machine Design Steps.

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Lecture X

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  1. Lecture X Algorithmic State Machines

  2. State Machine Design Steps 1) Create an algorithm, using pseudocode, to describe the desired operation of the device.2) Convert the pseudocode into an ASM chart.3) Design the datapath based on the ASM chart.4) Create a detailed ASM chart based on the datapath.5) Design the control logic based on the detailed ASM chart. 159.233 Computer Architecture

  3. ASM Charts Status lines (inputs) are tested in diagonal boxes. The two paths leading away from the test will be labeled with either T or F. Command lines (outputs), listed in the square boxes, are true (1) when the controller is in that state false (0) otherwise. Outputs listed in rounded boxes are only asserted if that path is taken 159.233 Computer Architecture

  4. ASM Charts • The state machine goes from one state to another on the tick of a clock Each state starts in a square box and lasts until you reach the next square box Everything within a state happens simultaneously 159.233 Computer Architecture

  5. ASM Charts 159.233 Computer Architecture

  6. Finite State Machine • How to implement an State Machine? 1. Use a register to store the present state number 2. Use some combinatorial logic to calculate what the next state should be. 3. On the tick of the clock transfer that new state into the register 4. repeat indefinitely 159.233 Computer Architecture

  7. Finite State Machine • Which state will it start in? • To make sure we don’t start in a state that could lead to self-destruction, we make sure we always start in state 0 • Hold ‘Reset’ line asserted when power is first applied, deassertingReset only after a little time has elapsed 159.233 Computer Architecture

  8. Bit-counter example Pseudocode: 159.233 Computer Architecture

  9. Bit-counter example • Design datapath • Need a n-bit left-to-right shift register with parallel load and Enable signals • Need a log2n-bit counter with parallel load and Enable • A n-input NOR gate to tell when A=0. 159.233 Computer Architecture

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