CSE 420/598 Computer Architecture Lec 11 – Chapter 2 - DS-Tomasulo

1. CSE 420/598 Computer Architecture Lec 11 – Chapter 2 - DS-Tomasulo Sandeep K. S. Gupta School of Computing and Informatics Arizona State University Based on Slides by David Patterson, Dave Culler, A. Lebeck

2. In News - Hard disk test 'surprises' Google • The report was compiled by Eduardo Pinheiro, Wolf-Dietrich Weber and Luiz Andre Barroso, and was presented to a storage conference in California last week. • “The impact of heavy use and high temperatures on hard disk drive failure may be overstated, says a report by three Google engineers.” • “There is a widely held belief that hard disks which are subject to heavy use are more likely to fail than those used intermittently. It was also thought that hard drives preferred cool temperatures to hotter environments.” • "However our results appear to paint a more complex picture. First, only very young and very old age groups appear to show the expected behaviour." • Surprising result: Lower temperatures are associated with higher failure rates • Implication: "This is a surprising result, which could indicate that data centre or server designers have more freedom than previously thought when setting operating temperatures for equipment containing disk drives,“ • Source: http://news.bbc.co.uk/2/hi/technology/6376021.stm?ls CSE420/598

3. Outline • ILP • Compiler techniques to increase ILP • Loop Unrolling • Static Branch Prediction • Dynamic Branch Prediction • Overcoming Data Hazards with Dynamic Scheduling • Tomasulo Algorithm • Conclusions CSE420/598

4. Advantages of Dynamic Scheduling • Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior • It handles cases when dependences are unknown at compile time • it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve • It allows code that was compiled for one pipeline to run efficiently on a different pipeline • It simplifies the compiler • Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling CSE420/598

5. HW Scheme: Instruction Parallelism • Key idea: Allow instructions behind stall to proceedDIVD F0,F2,F4 ADDD F10,F0,F8SUBD F12,F8,F14 • Enables out-of-order execution and allows out-of-order completion(e.g., SUBD) • In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) • Will distinguish when an instruction begins execution and when it completes execution; between two times, the instruction is in execution. • Note: Dynamic execution creates WAR and WAWhazards and makes exceptions harder True dependence – potential RAW hazard CSE420/598

6. Dynamic Scheduling Step 1 • Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue • Split the ID pipe stage of simple 5-stage pipeline into 2 stages: • Issue—Decode instructions, check for structural hazards • Readoperands—Wait until no data hazards, then read operands CSE420/598

7. A Dynamic Algorithm: Tomasulo’s • For IBM 360/91 (before caches!) •  Long memory latency • History: • 1966: scoreboarding in CDC6600, implementing limited dynamic scheduling • Three years later: Tomasulo in IBM 360/91, introducing register renaming and reservation station • Goal: High Performance without special compilers • Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations • This led Tomasulo to try to figure out how to get more effective registers — renaming in hardware! • Why Study 1966 Computer? • The descendants of this have flourished! • Dec Alpha 21264, Intel Pentium 4, AMD Opteron, IBM Power 5, … CSE420/598

8. Scoreboarding Merit Enables out-of-order execution and reduces stall cycles caused by RAW dependences • Use register result status table to detect WAW and RAW dependence between a newly fetched instruction and pending instructions • Record dependence into the FU status of scoreboard (in forms of Qj, Qk and Rj, Rk) • Keep an instruction waiting if it has dependences with pending instructions • When an inst writes result, wake updependent instructions by matching the inst’s FU index with Qj and Qk of every FU status entry CSE420/598

9. But Good Dynamic Sched. Needs More Better handling of WAR and WAW dependences • Scoreboarding: (1) Stalls issuing when WAW is detected; (2) Delay writing results when WAR is detected • Is it necessary to enforce WAR and WAW dependences? Better handling of structure hazards • Why stall pipeline when two instructions go to the same FU? (Particular a problem for memory/integer instructions) Better pipeline efficiency • Two extra cycles between the EXs of two dependent instructions – Need data forwarding More ILP beyond a basic block • Need speculative execution, branch predictions, and dynamic memory disambiguation CSE420/598

10. What Tomasulo Provides Better handling of WAR and WAW dependences • Use register renaming to remove WAR and WAW dependences – No stalls or delays anymore Better handling of structural hazards • Multiple reservation stations per FU – instruction is assigned to a reservation station Better pipeline efficiency • One extra (instead of two) between EXs of two dependent instructions Dynamic memory disambiguation • Enforce dependence between stores and loads Distributed scheduling logic • Register and RS status no longer centralized CSE420/598

11. Register Renaming • Register renaming (in hardware) • change register names to eliminate WAR/WAW hazards • one of the most elegant concepts in computer architecture • Key: think of architectural registers as names, not locations • can have more locations than names • dynamically map names to locations • map table holds the current mappings (name→location) • write: allocate new location and record it in map table • read: find location of most recent write by name lookup in map table • minor detail: must de-allocate locations appropriately CSE420/598

12. Register Renaming - Example CSE420/598

13. rd rs H/W Register Renaming (Conceptual) • Imagine if each write to register Ri created a new instance of that register • kth instance Ri.k • Later references to source register treated as Ri.k • Next use as a destination creates Ri.k+1 CSE420/598

14. value architected reg’s physical data reg rd rs H/W Register Renaming (less Conceptual) • Separate the functions of the register • Reg identifier in instruction is mapped to “physical register” id for current instance of the register • Physical reg set may be larger than allocated • What are the rules for allocating / deallocating physical registers? ifetch op rs rt rd renam op R[rs] R[rt] ? opfetch op Vs Vt ? CSE420/598

15. Reg renaming • Source Reg s: • physical reg P=R[s] • Destination reg d: • Old physical register R[d] “terminates” • R[d] :=get_free • Free physical register when • No longer referenced by any architected register (terminated) • No incomplete instructions waiting to read it • Easy with in-order • Out of order? ifetch op rs rt rd renam op R[rs] R[rt] ? opfetch op Vs Vt ? CSE420/598

16. Temporary renaming • Value “currently” bound to register is not present in the register file, instead… • To be produced by particular instruction in the datapath • Designated by function unit that will produce value, or • Nearest matching instruction ahead in the datapath (in-order), or • With an associated “tag” CSE420/598

17. Broadcasting result value • Series of instructions issued and waiting for value to be produced by logically preceding instruction. • Broadcast value and reg # to all the waiting instructions • One that match grab the value CSE420/598

18. Tomasulo Algorithm • Control & buffers distributed with Function Units (FU) • FU buffers called “reservation stations”; have pending operands • Registers in instructions replaced by values or pointers to reservation stations(RS); called registerrenaming; • Renaming avoids WAR, WAW hazards • More reservation stations than registers, so can do optimizations compilers can’t • Results to FU from RS, not through registers, over Common Data Busthat broadcasts results to all FUs • Avoids RAW hazards by executing an instruction only when its operands are available • Load and Stores treated as FUs with RSs as well • Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue CSE420/598

19. Tomasulo Organization FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB) CSE420/598

20. Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of Source operands • Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) • Note: Qj, Qk=0 => ready • Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register resultstatus—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. CSE420/598

21. Three Stages of Instr in Tomasulo Algo 1.Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2.Execute—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3.Writeresult—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available • Normal data bus: data + destination (“go to” bus) • Common data bus: data + source (“come from” bus) • 64 bits of data + 4 bits of Functional Unit source address • Write if matches expected Functional Unit (produces result) • Does the broadcast • Example speed: 3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for / CSE420/598

22. Code Example LD F6,34(R2) LD F2,45(R3) MULTI F0,F2,F4 SUBD F8,F6,F2 DIVD F10,F0,F6 ADD F6,F8,F2 LD1 LD2 SUBD MULTI ADD DIVD Operation latencies: load/store 2 cycles, Add/sub 2 cycles, Mult 10 cycles, divide 40 cycle CSE420/598

23. What to Observe • Whether some instructions can be issued=> pay attention to (1) RS (or load/store buffer) allocation (decode, RS allocation, source register renaming, dispatch); (2) change to register status (dest renaming) • Whether some instruction can be selected for execution (for every FU)=> Pay attention to instruction status change; the instr will finish in a given number of cycle • Whether some instruction is finishing execution=> Pay attention to instruction status change; the instr may write its result the next cycle • Whether some instruction is writing result=> Pay attention to (1) wakeup of the dependent instructions; (2) register status change; (3) RS de-allocation CSE420/598

24. Instruction stream 3 Load/Buffers FU count down 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter Tomasulo Example CSE420/598

25. Tomasulo Example Cycle 1 CSE420/598

26. Tomasulo Example Cycle 2 Note: Can have multiple loads outstanding CSE420/598

27. Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued • Load1 completing; what is waiting for Load1? CSE420/598

28. Tomasulo Example Cycle 4 • Load2 completing; what is waiting for Load2? CSE420/598

29. Tomasulo Example Cycle 5 • Timer starts down for Add1, Mult1 CSE420/598

30. Tomasulo Example Cycle 6 • Issue ADDD here despite name dependency on F6? CSE420/598

31. Tomasulo Example Cycle 7 • Add1 (SUBD) completing; what is waiting for it? CSE420/598

32. Tomasulo Example Cycle 8 CSE420/598

33. Tomasulo Example Cycle 9 CSE420/598

34. Tomasulo Example Cycle 10 • Add2 (ADDD) completing; what is waiting for it? CSE420/598

35. Tomasulo Example Cycle 11 • Write result of ADDD here? • All quick instructions complete in this cycle! CSE420/598

36. Tomasulo Example Cycle 12 CSE420/598

37. Tomasulo Example Cycle 13 CSE420/598

38. Tomasulo Example Cycle 14 CSE420/598

39. Tomasulo Example Cycle 15 • Mult1 (MULTD) completing; what is waiting for it? CSE420/598

40. Tomasulo Example Cycle 16 • Just waiting for Mult2 (DIVD) to complete CSE420/598

41. Faster than light computation(skip a couple of cycles) CSE420/598

42. Tomasulo Example Cycle 55 CSE420/598

43. Tomasulo Example Cycle 56 • Mult2 (DIVD) is completing; what is waiting for it? CSE420/598

44. Tomasulo Example Cycle 57 • Once again: In-order issue, out-of-order execution and out-of-order completion. CSE420/598

45. Why can Tomasulo overlap iterations of loops? • Register renaming • Multiple iterations use different physical destinations for registers (dynamic loop unrolling). • Reservation stations • Permit instruction issue to advance past integer control flow operations • Also buffer old values of registers - totally avoiding the WAR stall • Other perspective: Tomasulo building data flow dependency graph on the fly CSE420/598

46. Tomasulo’s scheme offers 2 major advantages • Distribution of the hazard detection logic • distributed reservation stations and the CDB • If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB • If a centralized register file were used, the units would have to read their results from the registers when register buses are available • Elimination of stalls for WAW and WAR hazards CSE420/598

47. The Use of Tag In Tomasulo, RS index is used as tag (tag is a modern term). • Tag is a unique identifier for a pending register result • Tag decouples the register result from the architectural register specifier • Tag removes WAR and WAW dependences without changing RAW dependences CSE420/598

48. Tomasulo Drawbacks • Complexity • delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon! • Many associative stores (CDB) at high speed • Performance limited by Common Data Bus • Each CDB must go to multiple functional units high capacitance, high wiring density • Number of functional units that can complete per cycle limited to one! • Multiple CDBs  more FU logic for parallel assoc stores • Non-precise interrupts! • We will address this later CSE420/598

49. And In Conclusion … #1 • Leverage Implicit Parallelism for Performance: Instruction Level Parallelism • Loop unrolling by compiler to increase ILP • Branch prediction to increase ILP • Dynamic HW exploiting ILP • Works when can’t know dependence at compile time • Can hide L1 cache misses • Code for one machine runs well on another CSE420/598

50. And In Conclusion … #2 • Reservations stations: renaming to larger set of registers + buffering source operands • Prevents registers as bottleneck • Avoids WAR, WAW hazards • Allows loop unrolling in HW • Not limited to basic blocks (integer units gets ahead, beyond branches) • Helps cache misses as well • Lasting Contributions • Dynamic scheduling • Register renaming • Load/store disambiguation • 360/91 descendants are Intel Pentium 4, IBM Power 5, AMD Athlon/Opteron, … CSE420/598