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Improved Regrowth of Self-Aligned Ohmic Contacts for III-V FETs

North American Molecular Beam Epitaxy Conference (NAMBE),8-11-2009. Improved Regrowth of Self-Aligned Ohmic Contacts for III-V FETs. Mark A. Wistey Now at University of Notre Dame mwistey@nd.edu. P. McIntyre, B. Shin, E. Kim Stanford University.

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Improved Regrowth of Self-Aligned Ohmic Contacts for III-V FETs

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  1. North American Molecular Beam Epitaxy Conference (NAMBE),8-11-2009 Improved Regrowth of Self-Aligned Ohmic Contacts for III-V FETs Mark A. Wistey Now at University of Notre Dame mwistey@nd.edu P. McIntyre, B. Shin, E. KimStanford University A.K. Baraskar, U. Singisetti, G.J. Burek, M.J.W. Rodwell, A.C. GossardUniversity of California Santa Barbara Funding: SRC mwistey@nd.edu

  2. Outline: Regrown III-V FET Contacts • Motivation for Self-Aligned Regrowth • Facets, Gaps, Arsenic Flux and MEE • MOSFET Results • Conclusion Wistey, NAMBE 2009

  3. High barrier III-V FET with Self-Aligned Regrowth: Self-aligned, no gaps Small Raccess High Velocity Channel Small Rc } Ultrathin 5nm doping layer High mobility access regions Gate High-k n+ Regrowth Channel In(Ga)P Etch Stop High doping: 1013 cm-2 avoids source exhaustion 2D injection avoids source starvation Dopants active as-grown Bottom Barrier Motivation for Regrowth: Scalable III-V FETs Classic III-V FET (details vary): { Large Area Contacts Gap Source Drain Gate • Advantages of III-V’s Large Rc Top Barrier or Oxide { Channel • Disadvantages of III-V’s Bottom Barrier Implant: straggle, short channel effects InAlAs Barrier Low doping Wistey, NAMBE 2009

  4. Gate • High growth temperature (>490°C): • Selective/preferential epi on InGaAs • No gaps near gate • Rough far field • High resistance MBE Regrowth: Bad at any Temperature? Source-Drain Regrowth Regrowth: 50nm InGaAs:Si, 5nm InAs:Si. Si=8E19/cm3, 20nm Mo, V/III=35, 0.5 µm/hr. 200nm Gap • Low growth temperature (<400°C): • Smooth in far field • Gap near gate (“shadowing”) • No contact to channel (bad) Gate Source-Drain Regrowth SiO2 Metals high-k Channel Wistey, NAMBE 2009 SEMs: Uttam Singisetti

  5. High Temperature MEE: Smooth & No Gaps 460C 490C Gap 540C 560C Smooth regrowth SiO2 dummy gate No gaps, but faceting next to gates SiO2 dummy gate Note faceting: surface kinetics, not shadowing. In=9.7E-8, Ga=5.1E-8 Torr Wistey, NAMBE 2009

  6. Shen & Nishinaga, JCG 1995 Fast surface diffusion = slow facet growth Slow diffusion = fast growth [111] faster SiO2 [100] • But gap persists [100] faster Shadowing and Facet Competition [111] Good fill next to gate. • Shen JCG 1995 says:Increased As favors [111] growth Slow diffusion = rapid facet growth Fast surface diffusion = slow facet growth SiO2 [100] [111]

  7. Gate Changes Local Kinetics 1. Excess In & Ga don’t stick to SiO2 2. Local enrichment of III/V ratio 4. Low-angle planes grow instead SiO2 or SiNx sidewall [100] Gate 3. Increased surface mobility • Diffusion of Group III’s away from gate

  8. Lowest arsenic flux → “rising tide fill” • No gaps near gate or SiO2/SiNx • Tunable facet competition Change of Faceting by Arsenic Flux • InGaAs layers with increasing As fluxes, separated by InAlAs. Increasing As flux InAlAs markers InGaAs SiO2 5x10-6 2x10-6 Cr 1x10-6 W 0.5x10-6 Original Interface (Torr) Growth conditions: MEE, 540*C, Ga+In BEP=1.5x10-7 Torr, InAlAs 500-540°C MBE. Wistey, NAMBE 2009

  9. [100] [100] SiO2 SiO2 [111] [111] • Lowest arsenic flux → “rising tide fill” • No gaps near gate or SiO2/SiNx • Tunable facet competition Control of Facets by Arsenic Flux • InGaAs:Si layers with increasing As fluxes, separated by InAlAs. Faceting [100] InAlAs markers SiO2 Increasing As flux [111] InGaAs SiO2 Conformal 5x10-6 2x10-6 Cr 1x10-6 W 0.5x10-6 Original Interface (Torr) Filling Growth conditions: MEE, 540*C, Ga+In BEP=1.5x10-7 Torr, InAlAs 500-540°C MBE. Wistey, NAMBE 2009

  10. Low-As Regrowth of InGaAs and InAs InGaAs InAs InAsregrowth InGaAs regrowth (top view) • Low As flux good for InAs too. • InAs native defects are donors.Bhargava et al , APL 1997 • Reduces surface depletion. • No faceting near gate • Smooth far-field too 4.7 nm Al203, 5×1012 cm-2 pulse doping In=9.7E-8, Ga=5.1E-8 Torr SEMs: Uttam Singisetti Wistey, NAMBE 2009

  11. 740 Ω-µm InAs Source-Drain Access Resistance 4.7 nm Al203, InAs S/D E-FET. • Upper limit: Rs,max = Rd,max = 370 Ω−μm. • Intrinsic gmi = 0.53 mS/μm • gm << 1/Rs ~ 3.3 mS/μm (source-limited case) • Ohmic contacts no longer limit MOSFET performance. Wistey, NAMBE 2009

  12. Conclusions • Reducing As flux improves filling near gate • Self-aligned regrowth: a roadmap for scalable III-V FETs • Provides III-V’s with a salicide equivalent • InGaAs and relaxed InAs regrown contacts • Not limited by source resistance @ 1 mA/µm • Results comparable to other III-V FETs... but now scalable Wistey, NAMBE 2009

  13. Acknowledgements • Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain... • McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre • Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer • Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm • SRC/GRC funding • UCSB Nanofab: Brian Thibeault, NSF Wistey, NAMBE 2009

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