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Latest comparative study results Distributed latency counters architecture proposal

Internal simulation meeting 04-06-2014 – Elia Conti OUTLINE. Latest comparative study results Distributed latency counters architecture proposal. Latest comparative study results (I). Simulation parameters: Hit rate : 2 GHz/cm 2 , trigger latency : 10 µs

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Latest comparative study results Distributed latency counters architecture proposal

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  1. Internal simulation meeting 04-06-2014 –Elia Conti OUTLINE • Latest comparative study results • Distributed latency counters architecture proposal

  2. Latest comparative study results (I) Simulation parameters: • Hit rate: 2 GHz/cm2, trigger latency: 10 µs • Full pixel matrix (hit generation): 512 x 512 pixels, pixel size 50 x 50 µm2 • Sensor thickness: 100 µm • Simulation run for 500,000 BX cycles  500,000 hit transactions generated  10,000 hit packets into PR buffer • Class of hits generated: tracks, track angle 90° with charge sharing, 43% hit pixels

  3. Latest comparative study results (II) • Simulation run for square (1x1-8x8) and rectangular (2x8-3x5-5x3-8x2)PR configurations with zero-suppressed FIFO architecture • Required number of buffer locations carried out for each configuration for both1% and 0.1% overflow probability • Total number of memory bits per pixel carried out with B-ID (16 bits) + full ToT(4 bits) memory organization, with/without hit map • Simulations results compared with statistical/analytical ones applied to symmetrical cluster model with “Average 4.22” distribution

  4. Latest comparative study results (III)

  5. Latest comparative study results (IV)

  6. Distributed latency counters architecture proposal (I) • Block diagram of hit processing section of the FE-I4 (T. Hemperek) • In practice equivalent to our pixel FSM • Receives comparator output • BC resolution • Generates Leading Edge (LE) • Generates Small hit Leading Edge (sLE) • Generates Trailing Edge (TE) • Generates ToT counter reset and enable (rst_cnt, en_cnt)

  7. Distributed latency counters architecture proposal (II) • Block diagram of ToT processing section of the FE-I4 (T. Hemperek) • Start ToT Counter • Global LE generation (orLE) • Reset memory signal generation (rst_mem) • Memory pointer selection (freeAddr) • Record reset/small in memory • Record neighbor • Record TOT value in memory

  8. Distributed latency counters architecture proposal (III) • Block diagram of memory management section of the FE-I4 (T. Hemperek) • Has to be defined • Selects free memory • Token management • Selects triggered memory during read • Enables outputs

  9. Distributed latency counters architecture proposal (IV) • Block diagram of latency memory of the FE-I4 (T. Hemperek) • Start/Reset latency counter • Indicate status (full) • Trigger (triggered) • Store/Recognize trigger ID

  10. Distributed latency counters architecture proposal (V) Pixel Unit Cell (PUC) MEMORY POINTER free_addr ..... • no timewalk correction logic ToT COUNTER ToT_out ToT MEMORY “ANALOG” FRONT-END PIXEL FSM enable/clear discr_out analog_hit r_edge read_data

  11. Distributed latency counters architecture proposal (VI) Pixel Region (PR) TRIGGER PUC 1,1 PUC 2,1 … PUC m,1 … PUC 1,2 PUC matrix ToT_out … … HITS PUC 1,n … … PUC m,n to derandom/ col. arbitration ..... rising_edge PR buffer ... MATCH/ DELETE free_addr ToA REGISTER MEMORY MANAGEMENT LATENCY COUNTER LATENCY COUNTER LATENCY COUNTER ToA ToA ToA read_data • arbitration section kept separated from trigger selection WRITEIN BUFFER EXT CNT

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