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Section 2 Computational Unit

DSP 技术与应用. Section 2 Computational Unit. ADSP-219x Block Diagram. 160 MHz Up to 64K words RAM 16K words ROM optional Boot ROM Multi-channel serial ports SPI and UART Ports Three 32-bit timers with PWM outputs 8- or 16-bit host port interface External memory interface

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Section 2 Computational Unit

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  1. DSP技术与应用 Section 2 Computational Unit

  2. ADSP-219x Block Diagram 160 MHz Up to 64K words RAM 16K words ROM optional Boot ROM Multi-channel serial ports SPI and UART Ports Three 32-bit timers with PWM outputs 8- or 16-bit host port interface External memory interface Up to 16 general purpose I/O 11 channel DMA controller On chip oscillator with PLL Flexible power management JTAG port for system test & debug Industrial grade 144 BGA and QFP packages ADSP-219x 16-bit Core Serial Port Serial Port Serial Port SPI SPI 16-bit Memory 24-bit Memory UART 8/16/32K RAM 8/16/32K RAM 16K x 24 ROM Timers Interrupt Controller DMA Controller Host Port System Clock (PLL) Parallel Port JTAG Scan Power Down Control 16 GPIO

  3. 32K x16 RAM 16K x 16 RAM 8K x 16 RAM External Memory Interface External Memory Interface External Memory Interface 16K x 24 RAM 32K x 24 RAM 8K x 24 RAM 16K x 24 ROM 16K x 24 ROM ADSP-2196 ADSP-2195 ADSP-2191 ADSP-219x Memory Maps • Simple migration from ADSP-2191 RAM device to low cost ROM devices • Pin-Pin compatible models allow users to: • migrate to smaller memory to reduce system costs or • move to larger memory models to increase end-product functionality

  4. ADSP-219x Block Diagram

  5. ADSP-2191 DSP Core Features • Fast arithmetic processing capabilities • Register File, ALU, Multiplier/MAC, Shifter • Single cycle arithmetic operations • No arithmetic Pipelining: • Register File -to- Arithmetic -to- Register File within one instruction cycle • Multiplier/MAC, Shifter support 40 bit results • Single-cycle Multiple data transfers • Two independent Data Address Generators (DAGs) support multiple data accesses in a single cycle • Circular buffer addressing supported in hardware • Both DAGs support circular buffering • Efficient program execution • Fast and efficient Program Sequencer • Supports looping in hardware, 8 levels deep

  6. Modified Harvard Architecture Internal Memory Data Memory Address Program Memory Address 24 DSP Core 24 Data Memory Data Program Memory Data 16 Cache 24 • Instructions are fetched over the PM bus unless in cache • Data Memory accesses have precedence over Program Memory data accesses • PM Bus conflicts occur when instruction fetch and PM data fetch are required in the same cycle (cache miss) • Block conflicts occur when both buses want to go to the same block in the SAME cycle

  7. How does the ADSP-2191 process it? I0=values;I4=constants;M0=1;M4=1; MR=0, MX0=dm(I0,M0), MY0=pm(I4,M4); cntr=1023;do myloop until ce; myloop:MR=MR+MX0*MY0(SS), MX0=dm(I0,M0), MY0=pm(I4,M4); MR=MR+MX0*MY0(SS); Harvard Architecture Allows Dual Data Fetch with implicit Pointer Updates in parallel Loop Control Hardware avoids software overhead Multiplication, Accumulation and Data Load in a real single cycle 32-Bit Multiplier Result Accumulation into a 40-Bit Register avoids need of overflow handling during loop

  8. Computational Units Section 2

  9. Binary Number Formatting

  10. Binary Notation in DSP's The ADSP-2100 Family of DSP's are fixed point processors that perform operations using a two's complement binary notation. Therefore, to efficiently program a DSP it is important to understand the following concepts: 1) Signed / Unsigned formats 2) Fractional / Integer formats 3) Ranges of Fractional Numbers 4) Hex to Decimal Conversions 5) Decimal to Hex Conversions

  11. Binary - Hexadecimal - Decimal Number Conversion Table Decimal Hexadecimal Binary 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

  12. Example of Data Formats 16 Bits of Data S/U U U U U U U U U U U U U U U U 0 15 Binary Bit Pattern Example System 0x0000 0V (- FULL SCALE) Unsigned 0xFFFF 5V (+ FULL SCALE) 0x8000 -5V (- FULL SCALE) Signed 0x0000 0V 0x7FFF 5V (+ FULL SCALE)

  13. 3 -2 2 1 0 -1 -(2 ) 2 2 2 2 2 2's Complement Representation For 2's complement representation, the scale factor for the sign bit of a number is seen as -(2)^(M-1) where M is the number of bits left of the binary point. For a 4.2 number, the sign scale is -(2^3). . Sign Bit Binary Point Example: 0101.01 = 0 * (-8) + 1 * (4) + 0 * (2) + 1 * (1) + 0 * (1/2) + 1 * (1/4) = 5.25 1101.01 = 1 * (-8) + 1 * (4) + 0 * (2) + 1 * (1) + 0 * (1/2) + 1 * (1/4) = - 2.75

  14. 2's Complement Representation Changing the sign of a 2‘s Complement Number-X = NOT(X) + 1 LSB ( invert all the bits and add an LSB) Example:-5.25 = -(b#0101.01) = NOT(b#0101.01) + b#0000.01 = b#1010.10 + b#0000.01 = b#1010.11 1010.11 = 1 * (-8) + 0 * (4) + 1 * (2) + 0 * (1) + 1 * (1/2) + 1 * (1/4) = -5.25

  15. Fractional versus Integer Notation • Fractional format is 1.15 notation S F F F F F F F F F F F F F F F • radix point • Integer format is 16.0 notation S I I I I I I I I I I I I I I I • radix point

  16. DSP is optimized for fractional notation DSP supports integer notation

  17. 16位定点数的m,n表示法 m表示符号位和整数部分，n表示小数部分，且m+n=16 因此 数的整数范围为（-2m-1,2m-1）， 小数的最小分辨率为2-n ADSP-219X在乘法运算时 使用1.15表示小数 使用16.0表示整数

  18. Ranges for 16 bit Formats FORMAT Largest Positive Largest Negative Value of 1 LSB Value (0x7FFF) Value (0x8000) (0x0001) In Decimal In Decimal In Decimal 1.15 0.999969482421875 –1.0 0.000030517578125 Fractional 2.14 1.999938964843750 –2.0 0.000061035156250 3.13 3.999877929687500 –4.0 0.000122070312500 4.12 7.999755859375000 –8.0 0.000244140625000 5.11 15.999511718750000 –16.0 0.000488281250000 6.10 31.999023437500000 –32.0 0.000976562500000 7.9 63.998046875000000 –64.0 0.001953125000000 8.8 127.996093750000000 –128.0 0.003906250000000 9.7 255.992187500000000 –256.0 0.007812500000000 10.6 511.984375000000000 –512.0 0.015625000000000 11.5 1023.968750000000000 –1024.0 0.031250000000000 12.4 2047.937500000000000 –2048.0 0.062500000000000 13.3 4095.875000000000000 –4096.0 0.125000000000000 14.2 8191.750000000000000 –8192.0 0.250000000000000 15.1 16383.500000000000000 –16384.0 0.500000000000000 16.0 Integer 32767.000000000000000 –32768.0 1.000000000000000

  19. Format Example = 32767 -> 5 V 0.999969482... -> 5 V = 16383 -> 2.5 V 0.499969482... -> 2.5 V = 0 -> 0 V 0.0000000... -> 0 V = -13107 -> -2.0 V -0.399993986... -> -2.0 V = -32768 -> -5.0 V -1.0000000.... -> -5.0 V +5 V 0x7FFF 1 2 0 V 0x0000 3 4 5 -5 V 0x8000 FORMAT 16.0 1.15 1) 0x7FFF 2) 0x3FFF 3) 0x0000 4) 0xCCCD 5) 0x8000

  20. Hexadecimal to Decimal Conversion (1.15 Format) There are two methods for converting hexadecimal numbers to decimal numbers. One is easy and one is hard. HARD WAY: Convert the hexadecimal number to binary. Place the binary point. Multiply each bit of the binary number by its associated scale factor. Example: Convert 0x2A00 to a 1.15 twos-complement decimal value 0x2A00 = 0.010 1010 0000 0000 = 2^-2 + 2^-4 + 2^-6 = 0.25 + 0.0625 + 0.015625 = 0.328125 = 0.33 = 1/3 EASY WAY: Use a calculator to convert the hexadecimal number to decimal. Divide the decimal number by 2^N where N is the number of bits to the right of the binary point. Example: Convert 0x2A00 to a 1.15 twos-complement decimal value 0x2A00 <=> 10752 / 2^15 = 10752 / 32768 = 0.328125

  21. Decimal to Hexadecimal Conversion (1.15 Format) There are two methods for converting Decimal Numbers to Hexadecimal numbers. One is easy, and one is hard. HARD WAY: Break the decimal number into its 2^N components. Example: Convert 0.8125 to a 1.15 twos-complement hexadecimal format. EASY WAY: Multiply the decimal number by 2^N where N is the number of bits to the right of the binary point. Then use a calculator to convert to hex. Example: Convert 0.8125 to a 1.15 twos-complement hexadecimal format 0.8125 * 2^15 = 0.8125 * 32768 = 26624 <=> 0x6800 0 -1 -2 -3 -4 -5 -6 -7 2 2 2 2 2 2 2 2 1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 0.8125 => => 0x6800 0 1 1 0 1 0 0 0

  22. Binary Notation Mini-Quiz • What is 0x4000 (1.15 format) in signed decimal notation? • What is 0x4000 (16.0 format) in signed decimal notation? • What is 0x4000 (0.16 format) in unsigned decimal notation? • What is .875 in hex 1.15 Format? • What is -.875 in hex 1.15 Format?

  23. Registers and Register File

  24. Register Groups Register File (DREG) Data Address Generator Interrupt Registers Bus Exchange (Px) Program Sequencer Page Registers Status Registers Core Registers Name explicitly to access System Control Registers (memory mapped) Use ‘reg(<addr>)’ to access DAG Base Address Registers Cache Control Register (CACTL) System Control Registers DMA Controller Registers Serial Port (SPORT) SPI Port EMI Registers Timer I/O Processor Registers (memory mapped) Use ‘io(<addr>)’ to access

  25. Core Register Subgroups • Arranged in logical groups to facilitate general instruction coding • DREG => data registers • G1REG => DAG1, interrupt control registers • G2REG => DAG2, loop counter registers • G3REG => status, page registers • Arranged in smaller logical groups for conditional instruction coding • XOPs and YOPs => specific subsets of DREG depending on type of computation unit (ALU/MAC/SHIFTER) • XOP => X operand for computational units • YOP => Y operand for computational units

  26. ADSP-219x Block Diagram

  27. Register File • The register file is the source and destination for most arithmetic operations • 16 x 16 bit registers • Complete set of background registers Input only MX0 MX1 AX0 AX1 MY0 MY1 AY0 AY1 SI Output/Input MR2 MR1 MR0 AR SR2 SR1 SR0

  28. Computational Registers • 16 x 16 Computational Registers in Register File (dreg) AR, AX0, AY0, AX1, AY1 MR2, MR1, MR0, MX0, MY0, MX1, MY1 SR2, SR1, SR0, SI • Additional Special Purpose Computational Registers AF ALU feedback, intermediate ALU results SE Shifter Exponent SB Shifter Block Exponent • Status Registers ASTAT Arithmetic Status MSTATMode Status

  29. Mode Status (MSTAT) Register

  30. Arithmetic Status (ASTAT) Register

  31. Register Access—Unconditional, Single-Function Instructions

  32. ADSP-219x Block Diagram

  33. Arithmetic Logic Unit (ALU) From Register File 16 16 MUX 16 AZ X Y AN CI AC ALU AF Register AV AR SAT AS AV LATCH AQ 16 16 AR Register In Register file

  34. Arithmetic Logic Unit ( ALU ) Functions • Basic arithmetic – addition, subtraction, add or subtract by a constant, increment/decrement, etc. • Logical operations – AND, OR, XOR, NOT. • Bit tests. • ABS, PASS, Division Primitives Features • Supports conditional instructions • Support for multiprecision math

  35. Arithmetic Logic Unit ( ALU )Example Instructions AR = MX0 +AY0; // Add the values in MX0 and AY0.Result is stored in AR AF = MR1 XOR AY1; // Perform an XOR with MR1 and AY1. Result is stored in AF IF GE AR = -AR; // Conditional instruction – if the previous ALU // operation resulted in a value greater than or equal// to zero, neg. AR. IF AV AR = AY1 +1; // Conditional instruction –overflow occurs flag is set, // increment the value in AY1. AR = MY0 + MY0; // The value of one register can be added by it self. AF = MY0 + MR1 + C;// Add the values MY0 and MR1 in respect of the carry // flag. AR = AX0 + AF; // Add the values in AX0 and AF. Store the result in AR // This instructions uses the XOP and YOP register subsets • AF is not in the register file. Must follow ALU conditional instruction register usage • The destination of the ALU result is either the AR or AF register. Only the specified destination register is updated

  36. Arithmetic Logic Unit ( ALU ) Unconditional ALU Instructions: Any register (DREGx) in the register file can be used as input AR = DREG1 + DREG2 ; AF DREG1 + C ; DREG1 + DREG2 + C ; DREG1 - DREG2 ; DREG1 - DREG2 + C - 1 ; DREG1AND DREG2 ; DREG1ORDREG2 ; DREG1XOR DREG2 ; NOTDREG ; PASSDREG1 ; //Add //Add with carry //Add with carry // Subtract //Subtract with borrow Logical Operations // Pass through ALU, set flags DREG1, DREG2 = DREG register set

  37. Arithmetic Logic Unit ( ALU ) Conditional ALU Instructions: [IF condition] AR = xop + yop ; AF xop + C ; xop + yop + C ; xop - yop ; xop - yop + C - 1 ; yop - xop ; yop - xop + C - 1 ; [IF condition] AR = xop AND yop; AF xop OR yop; xop XOR yop; NOT xop ; NOT yop ; [IF condition] AR = PASS xop ; AF yop ; constant ; xop + yop; xop = AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1 yop = AY0, AY1, AF, 0 //Add //Add with carry //Add with carry // Subtract //Subtract with borrow // Subtract yop/xop exchanged //Subtract with borrow Logical Operations // Pass XOP through ALU, set flags // Pass YOP through ALU, set flags // Pass a constant through ALU // to affect the status flags // addition updates the status flags

  38. Arithmetic Logic Unit ( ALU ) [IF condition] AR = - xop ; AF - yop ; ABS xop ; yop +/- 1 ; DIVS yop , xop ; DIVQ xop ; [IF condition] AR = TSTBIT n of xop; AF SETBIT CLRBIT TGLBIT n = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] [IF condition] AR= xop function constant; AF function= [+, -, AND, OR, XOR, NOT, ABS,PASS] constant = [0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,32767, -2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768] //makes the 2‘s complement of xop. //makes the 2‘s complement of yop. // absolute value of xop. // increment/decrement of yop. //division operation see advanced // instructions. // tests or modifies the bit n of the // register xop. // ALU operations using // constants.

  39. Arithmetic Status Register ASTATALU Flags Flag Name Definition AZ Zero True if ALU output equals 0 AN Negative Sign bit of ALU result. True if ALU output negative AV Overflow X-OR of carry outputs of 2 most significant adder stages. True if ALU overflows AC Carry Carry output from most significant adder stage AS Sign Sign of ALU input port. Affected only by ABS instruction AQ Quotient Quotient bit generated only by DIVS and DIVQ

  40. Arithmetic Logic Unit ( ALU ) condition codes Condition codes are based on values in ASTAT

  41. Arithmetic Logic Unit ( ALU ) Saturation • Sets ALU result to full scale positive or full scale negative if overflow or underflow occurs • Saturation mode enabled by executing ‘ena ar_sator ena AS’ (bit 3 of MSTAT) • Once enabled, affects every ALU operation with AR as the destination • AF will not saturate, (flags still get set) • Overflow or underflow determined by the following conditions • Overflow (AV)carry (AC)AR contents • 00ALU output • 01ALU output • 100x7ffffull-scale positive • 110x8000 full-scale negative

  42. Making the AV Flag Sticky • The ALU overflow flag AV can become a sticky flag by setting bit 2 in MSTAT • Making the AV flag sticky means once it is set it stays set until you explicitly clear it in software • Enable this feature by executing the instruction “ena av_latch”or“ena OL” • Disable this feature by executing the instruction “dis av_latch” or “ena OL” You can also write or read MSTAT directly

  43. Go to ALU Exercises

  44. ADSP-219x Block Diagram

  45. Multiply-Accumulator (MAC) From Register File 16 16 Multiplier 32 MV or SV ADD/Sub 40 40 MR2 | MR1 | MR0 or SR2 | SR1 | SR0 Register File

  46. Multiply-Accumulator (MAC) Functions • Multiplication • Multiplication/accumulate with addition, rounding optional • Multiplication/accumulate with subtraction, rounding optional • Rounding, saturating, or clearing result register Features • 40-bit dual accumulator registers (The result can either be put in register MR or register SR) • Multifunction computations can perform a MAC and load/store operations in a single cycle. • 8 bits of overflow protection (255 consecutive full-scale accumulates ) • Fractional & Integer support • Instructions can be conditional • Single-cycle context switch

  47. Example MAC Instructions MR = MX1 * MY0(SS); // multiply the value in MX1 and in MY0. Store the// result in the MR register. SR = AR * MY1(SS); // multiply the value in AR and MY1. Store the result // in the SR register. MR = MR + AR * MY1(SS); // multiply the value in AR and MY1 and add this// result to the previous value in MR. MR = 0; // clear the MR Accumulator and MV SAT MR; // Saturate MR if overflow flag was set. MR = MR; // can be used to effect the status flags (Check MV) IF EQ MR = MX0 * MY0(UU);// conditional instruction. If zero flag set by last ALU // operation, then condition true

  48. Unconditional MAC Instructions Multiply MR = DREG1 * DREG2 ( RND ) ; SR SS SU US UU Multiply with Add/Subtract MR = MR DREG1 * DREG2 ( RND ) ; SR = SR SS SU US UU S = Signed U = Unsigned RND = Round + - • Any register (DREGx) in the register file can be used as input

  49. Conditional MAC Instructions Multiply [IF condition] MR = XOP * YOP ( RND ) ; SR XOP SS SU US UU Multiply with Add/Subtract [IF condition] MR = MR XOP * YOP ( RND ) ; SR = SR YOP XOP SS SU US UU S = Signed U = Unsigned RND = Round + - XOP = MX0, MX1, AR, MR0, MR1, MR2, SR0, SR1 YOP = MY0, MY1, SR1, 0

  50. Placement of Binary Point in Multiplication • Binary Integer Multiplication M Bits Example: 16.0 x 16.0 => 32.0 x P Bits M+P Bits • Mixed/Fractional Multiplication M.N Bits Example: 1.15 x 1.15 => 2.30** 4.12 x 1.15 => 5.27 x P.Q Bits (M+P).(N+Q) Bits ** In fractional mode the result of a multiplication will be automatically left shifted by 1 bit resulting in a 1.31 format

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