Nascim

1. Nascim Next Generation Current-based,High Performance Simulation andVerification Solution

2. Agenda • Who we are • Our mission • Design issues and challenges • Nanometer design issues • Simulation and verification challenges • Issues with today’s tools and flows • The Next Generation Fast-SPICE Simulator OCP – IP Technology Pavilion

3. Nascentric’s Mission To deliver high-performance simulation and analysis solutions that address nanometer design issues related to timing, power and signal integrity. OCP – IP Technology Pavilion

4. Traditional Fast-SPICE introduced. Uses traditional SPICE analysis engine, but leverages replication found in hierarchical design Version 1.0 of SPICE is released into the public domain. Increased transistor counts & design complexity cause focus to shift to higher levels of abstraction(e.g, synthesis, STA, etc.) John Croix begins work on a new method for modeling devices and interconnect for transistor level analysis at UT Austin. Ron Rohrer begins work on transistor-level simulation at UC Berkeley. 1960’s 1972 1980’s 1990’s 2002 Industry Overview • Semiconductor design continues to get more complex • Design complexity far out pacing advances in productivity with respect to design tools • Focus has been on raising the level of abstraction to cope with design complexity • Sub-130nm effects require attention at the transistor level • Historical Perspective OCP – IP Technology Pavilion

5. A New Set of Design Issues • Rapid increase in design size • Existing solutions sacrifice accuracy by forcing the design to be cut • Interdependence of design constraints • Timing affects power, power affects thermal, thermal affects reliability… • Existing solutions optimize a single constraint at the expense of others • Nanometer effects are transient nature • Power and Thermal • Existing solutions interject 30-50% error in power estimation; • Existing solutions provide inaccurate simulation of leakage current; can result in thermal run away and catastrophic chip failure • Supply Voltage Variations (IR-drop) & Ground Bounce • Existing solutions can’t account for intentional and un-intentional IR-drop; can result in functional failures • Noise/Signal Integrity • Existing solutions fail to account for dynamic nature of noise on signal delay; can result in degraded system performance or functional failure NANOMETER EFFECTS OCP – IP Technology Pavilion

6. Design Complexity Impacting Productivity • 65nm node represents a major discontinuity in the design process • Not a linear increase in complexity • Requires new tools and new methodologies to be successful • Over 70% of internally developed tools focused on addressing nanometer effects • Leakage power consumes over 50% of overall power budget • Memory & random logic consume ~60% of dynamic and ~80% of leakage power • 70-80% of SoC designs fail 1st silicon • Over 70% of the design time is spent in verification • Still, 61% of all respins are due to incomplete verification • Multiple mask spins are common (>$1.5M per spin) • Time-to-market delayed by months • Existing Fast-SPICE not sufficient for 180nm and below • Sacrificing capacity can lead to functional failures • Need greater capacity without compromising accuracy • Need greater accuracy without sacrificing speed • Sacrificing accuracy can lead to catastrophic chip failures • Analyzing blocks out of context • Forced to settle for critical path analysis OCP – IP Technology Pavilion

7. Problems with Traditional Fast-SPICE • Translate Voltage to Derive Current Measurements • Evaluates voltage and translates into current • Error-prone and inaccurate for nanometer designs • Use a Monolithic Evaluation Engine • Transistors, interconnect, and so on • Overall performance limited due to large matrices and small time-step needed for all entities to converge • Has Capacity Limitations at Nanometer Processes • Traditional SPICE cannot handle large blocks • Traditional Fast-SPICE relies heavily on repetitive structures • Sacrifice Accuracy for Performance • Serious performance degradation at higher accuracy settings • Default settings are not optimal for nanometer designs • Determining performance trade-offs not straightforward OCP – IP Technology Pavilion

8. The Next Generation Fast-SPICE Simulator • Current-based models • Precisely reflect silicon behavior • Multiple Evaluation Engines • Engines optimized for netlist subcomponent types • Speed to Rapidly Simulate/Verify Large Designs • High speed dynamic transistor-level simulation without sacrificing accuracy • Capacity to Handle Higher Transistor Count/Parasitics • Efficient current-based model and intelligent memory usage • SPICE-Accurate Simulation and Analysis • Accurately measures currents/voltages simultaneously Key Characteristics OCP – IP Technology Pavilion

9. Modeling Define Geometry and building blocks Design and fabricate Test structures Note Measure both currents and voltages Perform measurements & obtain initial data Obtain and optimize circuit model Incorporate into Lib/Tech files Design Device Fail Design Rule Check Pass Design Accurate Model Source of All Design Data: The Device Model OCP – IP Technology Pavilion

10. HIGHER Speed • Multi-Engine Architecture* • Efficient Matrix Manipulation SPEED GREATER Accuracy • Current-based Models* • Topology-Aware Simulation* NASCIM ACCURACY CAPACITY LARGER Capacity • Optimized Models & Engines* • Intelligent Parasitic Handling* Introducing NascimThe Next Generation Fast-SPICE Simulator *patents-pending OCP – IP Technology Pavilion

11. Nascim’sMulti-Engine Architecture OCP – IP Technology Pavilion

12. NascimHigher Speed to Rapidly Simulate and Verify • Multi-Engine Architecture • Dedicated engines increase throughput • Eliminates accuracy vs. speed trade-off • Current-based Models • Enable fast matrix evaluations • Allow for efficient circuit partitioning • Advanced Interconnect Evaluation • Reduce computational overhead due to parasitics • Accurately simulate complex interconnect profiles SPEED OCP – IP Technology Pavilion

13. Traditional Fast-SPICE’s Monolithic Matrix Solution NascimComputation Reduction Approaches Basic Transistor Model Basic Parasitic Model Nascim’s Multi-Engine Matrix Solution OCP – IP Technology Pavilion

14. NascimLarger Capacity to Handle Nanometer Processes • Intelligent Parasitic Evaluation • Handles voluminous parasitic data • Results in minimal loss of accuracy • Current-based Models • Reduced number of equivalent circuits • Generate smaller matrices for computation • Efficient Memory Management • Limits allocation and de-allocation of memory • Reduces the size of system memory footprint CAPACITY OCP – IP Technology Pavilion

15. Transistor Device Inter-circuit Interconnect Inter-device Interconnect Basic Parasitic block Sub-block Sub-block Inter-block Interconnect Intelligent Parasitic Handling Unique parasitic profiles need selective and intelligent handling OCP – IP Technology Pavilion

16. Nascim Greater Accuracy with Current-based Models • Topology-Aware Simulation • Understands unique needs of circuit structures • Flexible BSIM model evaluation options • Current-based Models • Accurately reflect silicon behavior • Enable faster convergence • Enhances visibility into current flows • Critical for robust nanometer designs ACCURACY OCP – IP Technology Pavilion

17. SPICE Output AOI Output RCL Model Output Greater Accuracy with Current-based Models OCP – IP Technology Pavilion

18. Summary Nascim, the next generation Fast-SPICE technology, provides: • HIGHER Speed • Accelerates design cycle turnaround time • Enables multiple and comprehensive analyses • LARGER Capacity • Helps verify larger, more complex designs • Provides better functional coverage • GREATER Accuracy • Precisely reflects silicon behavior • Enable robust analyses with fewer iterations NASCIM OCP – IP Technology Pavilion

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