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Understanding MIPS Instruction Representation

Learn how to represent MIPS instructions as numbers in machine language, including R-Format, I-Format, and J-Format. Understand different instruction formats and fields for operands, addressing modes, and immediate values.

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Understanding MIPS Instruction Representation

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  1. Chap 2.4 - Instruction Representation Jen-Chang Liu, Spring 2006 Adapted from http://www-inst.eecs.berkeley.edu/~cs61c/

  2. Review • Instructions: Arithmetic: add, addi, sub Memory access: lw, sw Branch: beq, bne, j comparison: slt, slti, sltu, sltiu

  3. Review of Lab#2: memory access .globl main .data str: .asciiz "abcdABCD" .text main: … la $s1, str # $s1=str[0] lb $t2, 0($s1) addi $s1, $s1, 1 # $s1=str[1] lb $t2, 0($s1) str a b c d A B C D str[1] li $t0, 1 # i=1 lb $t2, $t0($s1) # str[i] Wrong!

  4. Hierarchy of Programming Languages Degree of abstraction operand operation High-level objects method Java arithmetic op. functions variables C Assembly registers instruction set Low-level machine registers binary operation code

  5. Q: How do we represent instructions in machine?

  6. Overview • Instructions as Numbers • R-Format • I-Format • Branch instruction: addressing mode • J-Format

  7. Instructions as Numbers (1/2) • Currently all data we work with is in words (32-bit blocks): • Each register is a word. • lw and sw both access memory one word at a time. • So how do we represent instructions? • Remember: Computer only understands 1s and 0s, so “add $t0,$0,$0” is meaningless. • MIPS wants simplicity: since data is in words, make instructions be words...

  8. 6 5 5 5 5 6 6 5 5 16 Instructions as Numbers (2/2) • One word is 32 bits, so divide instruction word into “fields”. • Each field tells computer something about instruction. • We could define different fields for each instruction, but MIPS is based on simplicity, so define 3 basic types of instruction formats: • R-format • I-format • J-format 26 6 opcode

  9. Instruction Formats • J-format: used for j and jal • I-format: used for instructions with immediates (含常數的指令) • lw and sw (since the offset counts as an immediate) • the branches (beq and bne) • (but not the shift instructions; later) • R-format: used for all other instructions • Registers as operands

  10. Overview • Instructions as Numbers • R-Format • I-Format • Branch instruction: addressing mode • J-Format 以暫存器為運算單位的指令

  11. 6 5 5 5 5 6 opcode rs rt rd shamt funct R-Format Instructions (1/5) • Define “fields” of the following number of bits each: Low-order bits high-order bits • For simplicity, each field has a name: • Important: Each field is viewed as a 5- or 6-bit unsigned integer, not as part of a 32-bit integer. • Consequence: 5-bit fields can represent any number 0-31, while 6-bit fields can represent any number 0-63. 每個field看做單獨的數字

  12. opcode rs rt rd shamt funct R-Format Instructions (2/5) • What do these field integer values tell us? • opcode: partially specifies what instruction it is (Note: This number is equal to 0 for all R-Format instructions.) • funct: combined with opcode, this number exactly specifies the instruction • Question: Why aren’t opcode and funct a single 12-bit field? • Answer: We’ll answer this later.

  13. opcode rs rt rd shamt funct R-Format Instructions (3/5) • More fields: • rs (Source Register): generally used to specify register containing first operand • rt (Target Register): generally used to specify register containing second operand (note that name is misleading) • rd (Destination Register): generally used to specify register which will receive result of computation

  14. opcode 000000 01001 rs 01010 rt 01000 rd shamt ? 100000 funct R-Format Example • MIPS Instruction: add $t0,$t1,$t2 => add $8,$9,$10 decimal representation: 0 9 10 8 32 ? binary representation:

  15. See p. A-54

  16. opcode rs rt rd funct shamt R-Format Instructions (4/5) • Notes about register fields: • Exactly 5 bits => 0~31 => indicate the register number • Final field: • shamt: This field contains the amount a shift instruction will shift by. Shifting a 32-bit word by more than 31 is useless, so this field is only 5 bits (so it can represent the numbers 0-31). • This field is set to 0 in all but the shift instructions.

  17. opcode rs rt rd shamt funct R-Format Example (cont.) • MIPS Instruction: add $t0,$t1,$t2 => add $8,$9,$10 decimal representation: 0 9 10 8 0 32 binary representation: 000000 01001 01010 01000 00000 100000 Hex: 0 1 2 a 4 0 2 0 Called a Machine Language Instruction

  18. Overview • Instructions as Numbers • R-Format • I-Format • Branch instruction: addressing mode • J-Format 以常數為運算單位的指令

  19. Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 I-Format Instructions (1/5) • What about instructions with immediates? • Ideally, MIPS would have only one instruction format (for simplicity): unfortunately, we need to compromise • 5-bit field only represents numbers up to the value 31: immediates may be much larger than this • Define new instruction format that is partially consistent with R-format ! R-format: c.f. add $t0, $t1, $t2 addi $t0, $t1, 2

  20. opcode 6 rs 5 rt 5 immediate 16 Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 I-Format Instructions (2/5) • I-format: • Again, each field has a name: Compared with R-format:

  21. Immediate 16 bits Opcode 6 Opcode 6 rs 5 rs 5 rt 5 rt 5 rd 5 shamt 5 funct 6 I-Format Instructions (3/5) • What do these fields mean? • opcode: same as before except that, since there’s no funct field, opcode uniquely specifies an I-format instruction • This also answers question of why R-format has two 6-bit fields to identify instruction instead of a single 12-bit field: in order to be consistent with other formats. I R

  22. opcode rs rt immediate I-Format Instructions (4/5) • More fields: • rs: specifies the only register operand (if there is one) • rt: specifies register which will receive result of computation (this is why it’s called the target register “rt”) addi $t0, $t1, 1

  23. opcode rs rt Immediate 16 bits I-Format Instructions (5/5) • The Immediate Field: • 16 bits  can be used to represent immediate up to 216 different values • addi, slti, sltiu: the immediate is sign-extended to 32 bits in real hardware operation • lw, sw: immediate = offset • lw $t0, 0($a0)

  24. opcode 001000 10110 rs 10101 rt 1111111111001110 immediate I-Format Example • MIPS Instruction: addi $s5,$s6,-50 => addi $21,$22,-50 decimal representation: 8 22 21 -50 binary representation: Hex: 2 2 d 5 f f c e

  25. I-Format Problems (1/3) • Problem 1: • What if immediates are too big to fit in the immediate field (16 bits only)? • We need a way to deal with a 32-bit immediate in any I-format instruction. • How to do this? addi $t0,$t0, 0x2BAB2DCD 16 bits 16 bits

  26. I-Format Problems (2/3) • Solution to Problem 1: • Handle it in software (assembler) • Don’t change the current instructions: instead, add a new instruction to help out • New instruction: lui register, immediate • stands for Load Upper Immediate • takes 16-bit immediate and puts these bits in the upper half (high order half) of the specified register • sets lower half to 0s reg. 16 16

  27. I-Format Problems (3/3) • Solution to Problem 1 (continued): • So how does lui help us? • Example: addi $t0,$t0, 0x2BAB2DCD becomes: lui $a0, 0x2BAB ori $a0, $a0, 0x2DCD add $t0,$t0,$a0 Why not : li $a0, 0x2BAB2DCD

  28. How to be an assembler? • Assembly code: .data .text main: bne $t0, $t1, End lui $t3, 0x2BAB ori $t3, $t3, 0x2DCD add $s0, $s1, $t3 End:

  29. Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 step 1 • Choose which formats they are? • Write down the formats and how many bits for each field R-format I-format Immediate 16 Opcode 6 rs 5 rt 5

  30. step 2 • Write down the encoding of registers

  31. Step 3: decide opcode

  32. step 4 • Fill the other fields

  33. opcode opcode opcode rs rs rs rt rt rt rd rd rd shamt shamt shamt funct funct funct opcode opcode rs rs rt rt immediate offset Peer Instruction Which instruction has same representation as 35ten? 1.add $0, $0, $0 2.subu $s0,$s0,$s0 3.lw $0, 0($0) 4.addi $0, $0, 35 5.subu $0, $0, $0 6.Trick question!Instructions are not numbers Registers numbers and names: 0: $0, .. 8: $t0, 9:$t1, ..15: $t7, 16: $s0, 17: $s1, .. 23: $s7 Opcodes and function fields (if necessary) add: opcode = 0, funct = 32 subu: opcode = 0, funct = 35 addi: opcode = 8 lw: opcode = 35

  34. Overview • Instructions as Numbers • R-Format • I-Format • Branch instruction: addressing mode • J-Format

  35. opcode rs rt immediate Branches: PC-Relative Addressing (1/5) Ex. beq $t0, $t0, Label • Use I-Format • opcode specifies beq ,bne • rs and rt specify registers to compare • What can immediate specify? • Immediate is only 16 bits • Label is 32-bitaddress in memory • So immediate cannot specify entire address to branch to.(16 bits 定址空間有限)

  36. Branches: PC-Relative Addressing (2/5) • How do we usually use branches? • Answer: if-else, while, for • Loops are generally small: typically up to 50 instructions (迴圈程式段落通常不大) • Function calls and unconditional jumps are done using jump instructions (j and jal), not the branches. • Conclusion: a single branch will generally change the PC by a very small amount.

  37. Branches: PC-Relative Addressing (3/5) • Solution: PC-Relative Addressing • 16-bit immediate= offset • Now we can branch +/- 215bytes from the PC, which should be enough to cover any loop. Target address: PC + offset … offset PC

  38. Branches: PC-Relative Addressing (4/5) • Note: Instructions are words, so they’re word aligned • So the number of bytes to add to the PC will always be a multiple of 4.(指令碼的位址都是四的倍數) • So specify the immediate in words. • Now, we can branch +/- 215words from the PC (or +/- 217bytes), so we can handle loops 4 times as large.

  39. Branches: PC-Relative Addressing (5/5) beq(bne) rs, rt, Label • Final Calculation: • If we don’t take the branch: PC = PC + 4 • If we do take the branch: PC = (PC + 4) + (immediate * 4) • Observations • Immediate field specifies the number of words to jump, which is simply the number of instructions to jump. • Immediate field can be positive or negative. • Due to hardware, add immediate to (PC+4), not to PC; will be clearer why later in course

  40. Branch Example (1/3) • MIPS Code: Loop: beq $9,$0,End add $8,$8,$10 addi $9,$9,-1 j Loop End: • Branch is I-Format: opcode = 4 (look up in table) rs = 9 (first operand) rt = 0 (second operand) immediate = ???

  41. Branch Example (2/3) • MIPS Code: Loop: beq $9,$0,End addi $8,$8,$10 addi $9,$9,-1 j Loop End: • Immediate Field: • Number of instructions to add to (or subtract from) the PC, starting at the instruction following the branch. • In this case, immediate = 3 PC+4 3 inst. *test this in PCspim, set bare machine in the setting

  42. 000100 4 01001 9 00000 0 0000000000000011 3 Branch Example (3/3) • MIPS Code: Loop: beq $9,$0,End addi $8,$8,$10 addi $9,$9,-1 j Loop End: decimal representation: binary representation:

  43. Big Idea: Stored-Program Concept • Computers built on 2 key principles: 1) Instructions are represented as numbers. 2) Therefore, entire programs can be stored in memory to be read or written just like numbers (data).

  44. Consequence #1: Everything Addressed • Since all instructions and data are stored in memory as numbers, everything has a memory address: instructions, data words • both branches and jumps use these • C pointers are just memory addresses • One register keeps address of instruction being executed: “Program Counter” (PC) • Basically a pointer to memory: Intel calls it Instruction Address Pointer, which is better

  45. Consequence #2: Binary Compatibility • Programs are distributed in binary form • Programs bound to specific instruction set • Different version for Macintosh and IBM PC • New machines want to run old programs (“binaries”) as well as programs compiled to new instructions

  46. R opcode target address I J opcode opcode rs rs rt rt rd immediate shamt funct Review • Machine Language Instruction: 32 bits representing a single MIPS instruction • Instructions formats are kept as similar as possible.

  47. 6 bits Target:26 bits Jump instruction • J-format • General address: 32 bits 26 bits PC 00 31… 28 word alignment

  48. opcode target address J-Format Instructions (1/5) • For branches, we assumed that we won’t want to branch too far, so we can specify change in PC. • beq, bne • For general jumps (j and jal), we may jump to anywhere in memory. • Ideally, we could specify a 32-bit memory address to jump to. • Unfortunately, we can’t fit both a 6-bit opcode and a 32-bit address into a single 32-bit word, so we compromise. J

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