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Understanding Gate Delay and Timing Models for Circuit Analysis

Explore gate propagation delay, timing components, and circuit analysis models to optimize cost/performance tradeoffs. Learn about asynchronous interactions and programmable implementation technologies. Dive into flip-flop timing and system level timing for effective circuit design.

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Understanding Gate Delay and Timing Models for Circuit Analysis

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  1. Overview • Part 1 – The Design Space • Part 2 – Propagation Delay and Timing • Propagation Delay • Delay Models • Cost/Performance Tradeoffs • Flip-Flop Timing • Circuit & System Level Timing • Part 3 – Asynchronous Interactions • Part 4 - Programmable Implementation Technologies

  2. 6-2 Gate Propagation Delay • Propagation delay is the time for a change on an input of a gate to propagate to the output. • Delay is usually measured at the 50% point with respect to the H and L output voltage levels. • High-to-low (tPHL) and low-to-high (tPLH) output signal changes may have different propagation delays. • High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. • An HL input transition causes: • an LH output transition if the gate inverts and • an HL output transition if the gate does not invert.

  3. Propagation Delay (continued) • Propagation delays measured at the midpoint between the L and H values

  4. Delay Models • Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay • Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur. Models typical electronic circuit behavior, namely, rejects narrow “pulses” on the outputs

  5. Delay Model Example A B A B: No Delay (ND) a b c d e Transport Delay (TD) Inertial Delay (ID) 0 2 4 6 8 10 12 14 16 Time (ns) Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns

  6. Calculate Circuit Delays 0.2 0.5 0.4 • Suppose gates with delay n ns are represented for n = 0.2 ns, n = 0.4 ns,n = 0.5 ns, respectively:

  7. Calculate Circuit Delays 0.2 0.5 0.4 0.4 A B S S Y A • Consider a simple 2-input multiplexer: • With function: • Y = B for S = 1 • Y = A for S = 0 • What is the delay of critical path? • “Glitch” is due to delay of inverter Y S B 0.9 ns 1.1 ns 0.2 ns

  8. Fan-out and Delay • The fan-out loading (a gate’s output) affects the gate’s propagation delay • Example 6-1:( page 324) • One realistic equation for tpd for a NAND gate with 4 inputs is: tpd = 0.07 + 0.021× SL ns • SL is the number of standard loads the gate is driving, i. e., its fan-out in standard loads • 4-input NOR gate—0.8 standard load • 3-input NAND gate—1.0 standard load • Inverter—1.0 standard load • For SL = 0.8+1+1, tpd = 0.129 ns, • What is the maximum standard loads? • If this effect is considered, the delay of a gate in a circuit takes on different values depending on the circuit load on its output.

  9. 6-3 Flip-Flop Timing • ts - setup time • th - hold time • tw - clockpulse width • Tp- - propa-gation delay • tPHL - High-to-Low • tPLH - Low-to-High • tpd - max (tPHL, tPLH)

  10. Flip-Flop Timing Parameters • ts - setup time • the time that inputs S and R or D must be maintained at a constant value prior to the occurrence of the clock transition • Master-slave - Equal to the width of the triggering pulse • Edge-triggered - Equal to a time interval that is generally much less than the width of the the triggering pulse

  11. Flip-Flop Timing Parameters • th - hold time • minimum time for which the inputs must not change after the clock transition that causes the output to change • Often is set to zero • tw-minimum clock pulse width to ensure that the master has time enough to capture the input values correctly • Tp- - propagation delay • Same parameters as for inverter gate except • Measured from clock edge that triggers the output to the output change instead from the inputs

  12. 6-4 Sequential Circuit Timing

  13. Circuit and System Level Timing • New Timing Components • tp - clock period - The interval between occurrences of a specific clock edge in a periodic clock • tpd,COMB - total delay of combinational logic along the path from flip-flop output to flip-flop input • tslack - extra time in the clock period in addition to the sum of the delays and setup time on a path • Must be greater than or equal to zero on all paths for correct operation

  14. Circuit and System Level Timing t p C t t t t pd,FF pd,COMB s slack (a) Edge-triggered (positive edge) t p C t t t t pd,FF pd,COMB slack s (b) Pulse-triggered (negative pulse) • Timing components along a path from flip-flop to flip-flop

  15. Circuit and System Level Timing • Timing Equations tp = tslack + (tpd,FF + tpd,COMB + ts) • For tslack greater than or equal to zero,tp≥ max (tpd,FF + tpd,COMB + ts)for all paths from flip-flop output to flip-flop input

  16. Example 6-2 • Suppose that all the flip-flops used are the same • tpd =0.2 ns • ts=0.1 ns • tpd,COMB=1.3 ns • tp=1.5 ns • tslack=-0.1 ns • tp is too small • tp >= 1.6ns • fmax=625 MHz

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