RGMII

1. RGMII MAC RX/TXSynchronous CAPTUREWITH 16802A AGILENT LOGIC ANALYZER Pascal GRISON Application Engineer

2. Objectives • Define a Logic Analyzer Configuration thatwouldenableSynchronous capture of RGMII MAC interface • Ideally Capture simultaneously TX and RX

3. RGMII MAC Interface details Bidirectional Full Duplex 125MHz Clock (for GbE) TX Side TXC (Dual EdgeClocking) TD[4] TD0 TD1 TD2 TD3 D3..DO sent on Rising TXC D7..D4 sent on falling TXC TX_CTL TX_EN sent on Rising TXC TX_ERR sent on falling TXC RX Side RXC (Dual EdgeClocking) RD[4] RD0 RD1 RD2 RD3 D3..DO sent on Rising RXC D7..D4 sent on falling RXC RX_CTL RXDV sent on Rising RXC RXERR sent on falling RXC

4. Capture TX Transactions NeedSynchronousSampling: State Mode Need Double EdgeClocking: ->State Samplingat 250MHz on 125MHz Clock -> Logic Analyzer -> Demux Mode to rebuild Data[8]

5. RGMII TX Timings TXD[3:0] & TXEN willbeClocked on Risingedge of TXC TXD[7:4] & TXERR willbeClocked on Fallingedge of TXC -> Weneed to use BothEdgesClocking (DEMUX Mode)

6. DemuxSampling Mode? In the Demultiplex state sampling clock mode, you can demultiplex data being probed by one pod into the logic analyzer memory that is normally used for two pods. Demultiplex mode uses the master and slave clocks to demultiplex the data. When the slave clock occurs, data captured on the pod is saved into the slave latch for the other pod in the pod pair. Then, when the master clock occurs, data captured on the pod, as well as the slave latch data, are saved in logic analyzer memory. As with master/slave mode, if multiple slave clocks occur before the next master clock, only the most recently acquired slave data is saved into logic analyzer memory. 2) -> TXCK FallingEdge 1) -> TXCK RisingEdge

7. Configure DEMUX Sampling Config Logic Analyzer as DEMUX STATE on TX CLOCK RisingEdgeis Salve Clock and Happend First FallingEdgeis Master Clock and Happend Second Master Clock Event activate Storage of one State Sample Up to 16M available (with Option 32)

8. Configure Bus SETUP Config of Logic Analyzer buses TXCK TXDATA as 8 bit bus TXDATA[3:0] & TXEN willbeClocked on Risingedge of TXC TXDATA[7:4] & TXERR willbeClocked on Fallingedge of TXC FULL DATA[7:0] + TXEN +TXERR willbestored in one memoryspace in logic Analyzer everyclock Cycle Up to 16M TX Packet Can beAcquired (with option 32M)

9. Overview of Logic Analyzer for TX DEMUX Current Config is the following: One Analyzer configured as one State Acquisition system to Demux and Acquire TX Packets

10. What About RX? WeNeed to Acquire TX & RX Packets RX Clockbehave in similar dual edge as TX Clock

11. RGMII RX Timings RXC isderivedfromreceived Ethernet Packets (Asynchronousfrom TXC) RXD[3:0] & RXDV willbeClocked on Risingedge of TXC RXD[7:4] & RXERR willbeClocked on Fallingedge of TXC -> Weneed to use BothEdgesClocking (DEMUX Mode)

12. How to Capture RX Packets RX ClockisAsynchronous to TX Clock RXDATA and RX_CTL are muxed TX Clock CANNOT beused to Acquired RX Data Need to definetwoindependant State Demux Acquisition System, one based on TXClock one on RXClock… Can we do this on a Single Logic Analyzer?

13. NowLet’s Split Your 68Ch Logic AnalyzerintoTwo 34Ch LogicAnalyzers Agilent LogicAnalyzers has unique capability to split themselves in Two!

14. Wenow dispose of TwoIndependantLogicAnalyzers in one Independant Channel Setup IndependantSalmpling Mode IndependantClocking Independant Triggers Independant Listing/Waveforms But Also Capable of Master/Slave Triggering Correlated Mesure thanks to IndependantTimestamps Common Listing/WaveformsCapability

15. Complete TX/RX DemuxSynchonoussampling System Overview TX Demux Master Trigger RX DemuxTriggedfrom TX Trigger Common TX/RX Listing Common TX/RX Waveforms Simultaneous 4GSa/s Timing oversampling (TimingZoom) available (capture 16µs around trigger)

16. Exemple of RGMII TX/RX Listing Demo Offline Data / Not real RGMII Capture

17. Scope –Logic AnalyzerTime CorrelatedMeasurements Use Logicanalyzer to trigger on RGMII Sequence of TX or RX Packets to Trigger Oscillosocpe Use Glitch or serial Trigger on Oscillosocpe to Trigger Logicanalyzer and findmatching RGMII Packet Get ALL Analog + Digital signalsDisplayed on single display Save ALL Analog + Digital signalsDisplayed on single file for post processing or Off-Lineanalysis Compatible with All current Agilent Scope and LogicAnalyzers Easy to Setup Lan based for data transfert & control 2 BNC Cablesfrom Triggers withautodeskewcapability AutomaticFastwaveform transfert from Scope to Logic Analyzer Markers correlatedbetween instruments

18. Exemple of Measure on DACDigital inputs correlatedwithAnalog Output

19. Questions & Answers?