Cadence Formal Verification 2003 Beijing International Microelectronics Symposium

1. Cadence Formal Verification2003 Beijing InternationalMicroelectronics Symposium C. Michael Chang Vice President, Formal Verification

2. Formal verification market leader Complete formal verification solution Proven technology - 1000s of design tapeouts Comprehensive ASIC vendor & foundry support >300 customers worldwide Functional 74% Noise 33% Clocking 31% Slow Path 31% Race Condition 24% Yield 23% Mixed Signal Intf 21% Power 14% October 2000 Collett International IR Drops 11% Firmware 10% 100% 0% 10% 20% 30% 40% 50% 60% 70% 80% Avant! + Synopsys Avant! + Synopsys Source: Dataquest, * EDAC Cadence Formal Overview • Half of all chips today require 1 or more re-spins • 74% of all re-spins are due to functional errors

3. Equivalence Checking (EC) Introduction Implementation Verification Gate: Post Synth, P&R Etc. RTL or Gate Conformal EC • Ensures consistency of two designs • Exhaustive verification using mathematical algorithms • Orders of magnitude faster than simulation • No test vectors required • Pinpoints errors quickly • Simplifies analysis and debug of implementation errors

4. Custom logic, I/O cells Memory Datapath Random Logic Memory Memory Custom logic, I/O cells Custom logic, I/O cells Datapath Memory Random Logic Datapath Memory Memory Memory Memory Datapath Custom logic, I/O cells Conformal SolutionComprehensive Equivalence Checking Solution EC for Random Logic Verifies synthesized logic EC for Complex Datapath Verifies compiled datapath EC for Digital Custom Verifies custom logic, IO cells, libraries EC for Embedded Memory Verifies custom memories EC for Layout Verifies physical integration Clock Domain Crossing Checks Verifies clock synchronization Semantic & Structural Checks Verifies buses and synthesis pragmas

5. RTL Logic Synthesis Logic Optimization Test Insertion Clock Synthesis Floor Planning Placement Routing P&R Optimization ECOs Conformal SolutionImplementation Verification • Used throughout the implementation process • Independently developed technology • Production proven on 1000s of designs • Best performance “Conformal by far blows away Formality in speed and capacity.” - Bob Lawrence, Agere Systems Conformal Equivalence Checker Conformal ensures implementation equivalence

6. Datapath Synthesis RTL Gate Equivalence Checked Conformal EC Conformal SolutionExtends EC to Complex Datapath • Trends indicate increased usage of advanced datapath optimization • Used to create high performance and area optimized circuits • Conformal provides formal verification solution for complex datapath • Exhaustive verification • Magnitudes faster than simulation • Easier to pin-point errors and debug "Verifying datapath circuits has been very difficult and time consuming in the past, but we have found Conformal DP to be very efficient in comparing different types of datapath circuits." Hiroshi Furukawa, System-on-a-Chip Design Division of NEC Micro Systems

7. Conformal Solution Complex Datapath Support Operator Merging C • Handles advanced datapath optimization techniques including operator merging and advanced pipelining • Flexible – Flattened or hierarchical • Supports wide variety of datapath architectures from many datapath synthesis vendors A B C B A X + Merged Operator Y Y Advanced Pipeline Support First EC tool to successfully verify complex datapath circuits

8. RTL Model Final Circuit Equivalence Checker Circuit Abstraction Conformal EC EC LVS • Physical Design • Layout integration • Circuit optimization • Netlist Conversion • GDS edits Gate Model Final GDS Conformal Solution Closing the RTL to GDS Verification Gap Conformal ensures RTL to GDS equivalency

9. RTL With MEM Primitive Cadence Memory Primitive Conformal Solution Extends EC to Memories Spice Netlist RTL Equivalence Checked Memory Primitives Circuit Abstraction Equivalence Checker Conformal EC Solution • Targets customer designed embedded memories • Exhaustive verification without vectors • Verifies complex control, scan, BIST, etc… • Magnitudes faster than simulation • Supports RAM (single & multi-port), CAM (binary & ternary), and register files

10. Conformal SolutionProviding a Safer EC Environment • Complements EC flow • Automatic extraction and verification: • Clock Domain Crossing (CDC): • Clock synchronization & data transfer validation • Semantics: • Verification of synthesis pragmas & assumptions • Structural: • Implementation checks including bus & tri-state • Can validate checks that don’t exist in RTL • Finds difficult implementation bugs

11. Conformal detects Clock topology problems Metastability problems Potential CDC glitches Divergent synchronizers Graycode violations Data stability violations Conformal Solution Clock Domain Checking CLK A a CLK B • Pinpoint problems quickly • Automatic detection of clock domains and crossings • Structural verification of multiple clock domain synchronization • Functional verification for data stability violations • Automates error-prone manual post static timing analysis process • Reduces risk of clock related re-spins • Prevents late clock related iterations in the design cycle

12. RTL always @ (a or b or s) begin case (s[1:0])//synthesis full_case 2’b01: q = a; 2’b10: q = b; endcase end Gate-level a q b s[1] Simulation 1 0 1 0 s[1] 1 1 0 1 s[0] a b a RTL: q a b a Gate: q b a Conformal Solution Semantic Checks • Conditions that may create mismatches between RTL and gate-level simulations • Full case • Parallel case • X-assignment • Range Overflow • Conformal checks if unexpected conditions can exist in design: s[1:0] == {0,0}, s[1,0] == {1,1} • Finds functional mismatches that are otherwise missed or detected only by gate level simulation late in design cycle • Equivalency can not find this type of error • EC follows synthesis interpretation Synthesis Conformal finds semantic corner-case bugs earlier

13. 0 ... 1 q ... 1 ... 1 ... Conformal Solution Structural Checks • Class of bugs typically found late in design cycle, if at all • May not be present in “RTL” , scan insertion errors • Introduced during design integration • Introduced during implementation and ECOs • Bus Checks • Bus contention Bus or net driven by conflicting data • Bus floating Bus is not driven by any signal • Tri-state Stuck-at problem with tri-state driver enable • Set / Reset Check Set and Reset on at the same time • Multi-port Latch Check Multi-port latches loaded with conflicting values Sequential analysis for bus contention Bus errors are a common source of silicon failure Conformal finds all structural consistency problems both during design and implementation cycles

14. Conclusion • The verification problem continues to grow at an exponential rate • Simulation-based techniques cannot meet the challenge alone • Formal analysis is a critical requirement for thorough verification • Equivalence checking is used throughout the implementation process • Conformal offers the only comprehensive EC solution for complex SoCs • Conformal technology was developed independently to maintain verification integrity