CpE 442 Introduction To Computer Architecture Lecture 1

1. CpE 442 Introduction To Computer Architecture Lecture 1 Instructor: H. H. Ammar These slides are based on the lecture slides provided with the course text book specified in the course syllabus The original slides were prepared by D. Patterson et al, UC Berkeley.

2. Overview of Today’s Lecture • Course Overview • Levels of Representation • Levels of Organization

3. Course Overview Computer Design Computer Hardware Design ° Machine Implementation ° Logic Designer's View ° "Processor Architecture" ° "Computer Organization” “Construction Engineer” Instruction Set Deign ° Machine Language ° Compiler View ° "Computer Architecture" ° "Instruction Set Processor" "Building Architect"

4. Instruction Set Architecture . . . the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, and Brooks, 1964 SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions

5. Organization ISA Level -- Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALUs, Shifters, Logic Units, etc. -- Ways in which these components are interconnected -- nature of information flows between components -- logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level Description FUs & Interconnect Logic Designer's View

6. What is "Computer Architecture” ?A system concept integrating software, hardware, and firmwareto specify the design of computing systems ° Co-ordination of levels of abstraction Application Operating System Compiler Instruction Set Architecture Instr. Set Proc. I/O system Digital Design Circuit Design ° Under a set of rapidly changing Forces

7. Forces on Computer Architecture Programming Technology Languages Applications Computer Architecture Operating Systems History

8. Technology: Microprocessor Logic Density Memory: 4x every 3 years

9. Performance Trends Supercomputers Mainframes Minicomputers Microprocessors

10. CPU and LAN Performance Relative Performance CPU 1000 100 10 1 LAN DEC Alpha 1 Gb ATM MIPS M/120 100 Mb FDDI 10 Mb Year 1980 1985 1990 1995 2000

11. Overview of Today’s Lecture • Course Overview • Levels of Representation • Levels of Organization

12. Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; High Level Language Program lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Compiler Assembly Language Program Assembler Machine Language Program 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Interpretation Control Signal Spec

13. MIPS R3000 Instruction Set Architecture • Instruction Categories • Load/Store • Computational • Jump and Branch • Floating Point • coprocessor • Memory Management • Special R0 - R31 PC HI LO Instruction Format OP rs rd sa funct rt OP rs rt immediate OP target

14. Measurement and Evaluation Architecture is an iterative process -- searching the space of possible designs -- at all levels of computer systems Creativity Cost / Performance Analysis Good Ideas Mediocre Ideas Bad Ideas

15. Course Overview (cont) Computer Design Computer Hardware Design ° Machine Implementation\ ° Logic Designer's View ° "Processor Architecture" ° "Computer Organization" “Construction Engineer” Instruction Set Deign ° Machine Language ° Compiler View ° "Computer Architecture" ° "Instruction Set Processor" "Building Architect" Few people design computers! Very few design instruction sets! Many people design computer components. Very many people are concerned with computer functions, in detail.

16. So what's in it for you ? • In-depth understanding of the inner-workings of Computing Systems, their evolution, and trade-offs present at the hardware/software boundary. • Insight into fast/slow operations that are easy/hard to implementation hardware • Understanding of the design process in the context of a large complex Computing Systems design. • Functional Spec --> Control & Datapath Design-- --> Physical implementation

17. SPARCstation 20 MBus Slot 1 SBus Slot 1 SBus Slot 3 MBus Slot 0 SBus Slot 0 SBus Slot 2 Example Architecture: The SPARCstation 20 Memory SIMMs Memory Controller Memory Bus MBus Disk Tape SBus SCSI Bus MSBI SEC MACIO Keyboard Floppy External Bus & Mouse Disk

18. Overview of Today’s Lecture • Course Overview • Levels of Representation • Levels of Organization

19. Levels of Organization SPARCstation 20 Computer SPARC Processor Memory Devices Control Input Datapath Output

20. SPARCstation 20 The Underlying Network Memory Bus Memory Controller Standard I/O Bus: SCSI Bus Processor Bus: MBus Sun’s High Speed I/O Bus: SBus MSBI SEC MACIO Low Speed I/O Bus: External Bus

21. SPARCstation 20 MBus Slot 1 MBus Slot 0 Processor and Caches MBus Module SuperSPARC Processor MBus Registers Datapath Internal Cache Control External Cache

22. SPARCstation 20 SIMM Slot 0 SIMM Slot 1 SIMM Slot 2 SIMM Slot 3 SIMM Slot 4 SIMM Slot 5 SIMM Slot 6 SIMM Slot 7 DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Memory Memory Bus Memory Controller DRAM SIMM

23. SPARCstation 20 SBus Slot 1 SBus Slot 3 SBus Slot 0 SBus Slot 2 Input and Output (I/O) Devices • SCSI Bus: Standard I/O Devices • SBus: High Speed I/O Devices • External Bus: Low Speed I/O Device Disk Tape SBus SCSI Bus SEC MACIO Keyboard Floppy External Bus & Mouse Disk

24. SPARCstation 20 Standard I/O Devices • SCSI = Small Computer Systems Interface • A standard interface (IBM, Apple, HP, Sun ... etc.) • Computers and I/O devices communicate with each other • The hard disk is one I/O device resides on the SCSI Bus Disk Tape SCSI Bus

25. SPARCstation 20 SBus Slot 1 SBus Slot 3 SBus Slot 0 SBus Slot 2 High Speed I/O Devices • SBus is SUN’s own high speed I/O bus • SS20 has four SBus slots where we can plug in I/O devices • Example: graphics accelerator, video adaptor, ... etc. • High speed and low speed are relative terms SBus

26. SPARCstation 20 Slow Speed I/O Devices • The are only four SBus slots in SS20--”seats” are expensive • The speed of some I/O devices is limited by human reaction time--very very slow by computer standard • Examples: Keyboard and mouse • No reason to use up one of the expensive SBus slot Keyboard Floppy External Bus & Mouse Disk

27. 1. The HASE Architecture Simulation Environment2. The New Compiler Technology simulation (to beshown in class)3. MIPS Assembly Language Simulators a. SPIM A MIPS32 Simulatorhttp://pages.cs.wisc.edu/~larus/spim.html b. MARS (MIPS Assembler and Runtime Simulator)http://courses.missouristate.edu/kenvollmar/mars/ Computer Architecture Simulation Tools

28. Summary • All computers consist of five components • Processor: (1) datapath and (2) control • (3) Memory • (4) Input devices and (5) Output devices • Not all “memory” are created equally • Cache: fast (expensive) memory are placed closer to the processor • Main memory: less expensive memory--we can have more • Input and output (I/O) devices has the messiest organization • Wide range of speed: graphics vs. keyboard • Wide range of requirements: speed, standard, cost ... etc. • Least amount of research (so far)