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CPEG 421/621 - Spring 2008

CPEG 421/621 - Spring 2008. Compiler Design: The Software and Hardware Tradeoffs. Instructor: Prof. Guang R. Gao Office: 312 DuPont Hall Phone: 831-8218 email: ggao@eecis.udel.edu Co-instructor: Dr. Haiping Wu Office: 306 DuPont Hall Phone: 831-0332

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CPEG 421/621 - Spring 2008

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  1. CPEG 421/621 - Spring 2008 Compiler Design:The Software and Hardware Tradeoffs \course\cpeg421-08s\Topic-1.ppt

  2. Instructor: Prof. Guang R. Gao Office: 312 DuPont Hall Phone: 831-8218 email: ggao@eecis.udel.edu Co-instructor: Dr. Haiping Wu Office: 306 DuPont Hall Phone: 831-0332 email: hwu@capsl.udel.edu TA: Thomas St John email: stjohn@capsl.udel.edu webpage: http://www.capsl.udel.edu/courses/cpeg421/2008/ Admin. Information \course\cpeg421-08s\Topic-1.ppt

  3. Important Dates May 14(Mon.) : Tentative: quiz May 16 (Wed.) : project report due Course work will carry the following weights towards your final grade: Homework, Lab and class Participation: 25% Quiz: 45% Project: 30% \course\cpeg421-08s\Topic-1.ppt

  4. References 1. A set of papers - to be assigned 2. Books: A. Aho, M. S. Lam, R. Sethi and J. Ullman, Compilers: Principles, Techniques and Tools (The Dragon Book, second edition), Addison Wesley, 2006 Other references: see course page \course\cpeg421-08s\Topic-1.ppt

  5. 3. Journals IEEE Computer Transactions on Computers Concurrency Transactions on Parallel and Distributed Systems ACM TOPLAS - Transactions on Programming Languages and Systems Transaction on Computer Systems JPDC Journal of Parallel and Distributed computing JSC Journal of Supercomputing JPP International Journal of Parallel Programming PC Parallel Computing (North-Holland) JPL J. of Programming Languages Other References \course\cpeg421-08s\Topic-1.ppt

  6. 4. Conference Proceedings PLDI ACM Symposium on Programming Language Design and Implementation POPL ACM Symposium on Principles of Programming Languages PPOPP ACM Symposium on Principles and Practice of Parallel Programming ICPP International Conference on Parallel Processing ICS International Conference on Supercomputing LCPC Intern. WS. on Languages and Compilers for Parallel Computing PACT Parallel Architectures and Compilation Techniques (since 1994) IPDPS International Parallel and Distributed Processing Symposium EUROPAR European Parallel Processing Conferences MICRO ACM/IEEE Symposium on Microarchitectures ISCA ACM/IEEE International Symposium on Computer Architecture ASPLOS ACM Symposium on Architecture Support for Program Languages and Operating Systems Other Reference \course\cpeg421-08s\Topic-1.ppt

  7. Major Topics • Topic 1: An Overview on Compiler Design • Topic 2: Compiler Front-End and IR • Topic 3: Run-time Environment • Topic 4: Middle-End and Optimizations • Topic 5: Middle-End Optimization: Loop Nest Optimizations • Topic 6: Back-End Optimization: Code Generation • Topic 7: Advanced Optimization • Topic 8: Compiler and Architecture Co-Design \course\cpeg421-08s\Topic-1.ppt

  8. Processor architecture design flow Compiler structure and design flow Code generation design flow Foundations for Compiler Design \course\cpeg421-08s\Topic-1.ppt

  9. Why Study Compilers? • • Influences on programming language design • • Influences on computer design • • Compiling techniques are useful for software development ─ Parsing techniques are often used ─ Learn practical data structures and algorithms ─ Basis for many tools such as text formatters, structure editors, silicon compilers, design verification tools,… Writing a compiler requires an understanding of almost all important CS subfields \course\cpeg421-08s\Topic-1.ppt

  10. Architecture Models • Architecture features/models • Simultaneous multithreading • Vector units. SIMD • Instructional Level Parallelism (ILP) • superscalar • VLIW • Chip multiprocessing (CMP, multi-core, etc.) What is the impact of these ideas on compilers? \course\cpeg421-08s\Topic-1.ppt

  11. ISA Simulator System Level Simulator Arch./Compiler and System Software Design Toolset Processor Architecture Design Flow Diagram Instruction Set Architecture Design (Microarchitecture Design-I) System-Level Design Compiler Design Hardware Design RTL Level Design (Microarchitecture Design II) Code Optimizer Switch Level Design Code Generator Switch Level Simulator RTL Level Simulator Circuit Level Simulator Circuit Level design Toolchain - Intel VTune™ - IBM Performance Evaluator Debugger HDL (VHDL or Verilog) \course\cpeg421-08s\Topic-1.ppt

  12. A Good Compiler Infrastructure Needed – A modern View Front end Interprocedural Analysis and Optimization Good IR Loop Nest Optimization and Parallelization Global (Scalar) Optimization Middle-End Backend Code Generation \course\cpeg421-08s\Topic-1.ppt

  13. Middle-End Optimization • Flow Analysis • Control flow analysis • Dataflow analysis • Global scalar optimization • Loop nest optimization • Advanced topics: • Static Single Assignment form (SSA) • Application of SSA to scalar optimization \course\cpeg421-08s\Topic-1.ppt

  14. Backend Optimization (I) • Instruction selection • Instruction scheduling • Register allocation • Others \course\cpeg421-08s\Topic-1.ppt

  15. Backend Optimization (II) • Loop optimization and scheduling • Software pipelining \course\cpeg421-08s\Topic-1.ppt

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