Speaker : Utku Özcan ASIC Designer, R&D, Netaş, Turkey

1. A Novel Parametric ATM Adaptation Layer 1 Bridging Between PCM and ATM Speaker: Utku Özcan ASIC Designer, R&D, Netaş, Turkey Designers: Utku Özcan,ASIC Designer İsmail Hakkı Topçu, Hardware Designer Ömer Aydın, Senior System Engineer {ozcan, topcu, aydin}@netas.com.tr

2. ATM (Asynchronous Transfer Mode) ATM (Asynchronous Transfer Mode): A most recent network technology - voice, image and data transfer on the same network - support of users with different features - support high transfer rates between end users ATM network

3. ATM (Asynchronous Transfer Mode) User information is carried in 53 byte packets called ATM cells on an ATM network - user information acquired in 53 byte packets On the Transmitter - packets reassembled and sent to users On the Receiver

4. ATM Cell Network element Network element AAL1 Header (1 byte) ATM Header (5 bytes) ATM cell payload (47 bytes)

5. Preparation of ATM to the users End users described by QoS (Quality of Service) On ATM Users tell the network what kind of transfer will exist Network will be programmed for best performance according to this set of information QoS 1 QoS 2

6. ATM Network General Architecture An ATM network is implemented mostly as hardware AAL users are implemented mostly as software AAL user AAL user AAL Layer (AAL) AAL Layer (AAL) ATM Layer (ATM) ATM Layer (ATM) Physical Layer (PHY) Physical Layer (PHY)

7. GFC VPI VPI VCI VCI VCI PTI CLP HEC AAL1 Header ATM cell payload byte 1 ATM cell payload byte 2 ... ... ATM cell payload byte 47 ATM QoS types Basic QoS types CBR (Constant Bit Rate) VBR (Variable Bit Rate) Some of QoS data carried in ATM Header 7 4 3 0 QoS List

8. ATM Adaptation Layer AAL ATM Adaptation Layer It serves as an interface between the users and the ATM network 5 different types of AAL are defined in ITU-T Standarts Most common AAL1 types AAL1: used in CBR type QoS (e.g. POTS) AAL5: used in VBR type QoS (e.g. Internet) AAL1 AAL5

9. ATM Adaptation Layer 1 (AAL1) AAL1 ATM Adaptation Layer 1 - a connection based layer protocol - support to conventional phone networks - numerous researches on AAL1 - realtime voice or image transmission - ISDN network on ATM network

10. ISDN Terminal ISDN Terminal AAL Layer (AAL) AAL Layer (AAL) ATM Layer (ATM) ATM Layer (ATM) Physical Layer (PHY) Physical Layer (PHY) ISDN facility on ATM Support of 64 kbps voice traffic: ISDN over ATM Result: ISDN uses ATM advantages

11. ISDN Rate Adaption and AAL1 ISDN supports users with 64 kbps rate Today, most users have a bandwidth of lower than 64 kbps Rate adaption necessity: ITU-T X.30/V.110 standards All state-of-the-art AAL1 applications support new systems Support of old systems: X.30/V.110 feature in AAL1 Conventional AAL1 ?

12. NETAAL1: Netaş’ AAL1 Solution NETAAL1 Netaş AAL1 Solution - support to every kind of user - ISDN compatibility - user variety taking advantage of ATM Our AAL1

13. General Architecture of AAL1 AAL1 user data AAL1 user data Convergence Sublayer ... ... CSI output SC Output CSI Analysis SC Analysis 1 bit 3 bits 1 bit 3 bits AAL1 Header Correction-Detection Segmentation & Reassembly sublayer AAL1 Header Calculator 47 bytes 47 bytes 1 byte 1 byte AAL1 PDU (48 bytes) AAL1 PDU (48 bytes) Transmitter side Receiver side ATM Layer ATM Layer

14. Main Functions of AAL1 Convergence Sublayer, CS Transmitter Side: - acquires user data in 47 byte packets - assigns a Sequence Count, SC for every 47 byte packet - prepares Convergence Sublayer Indication (CSI) Receiver Side: - sends 47 byte packets to the user - analyzes the sequence of 47 byte packets - analyzes timing information (CSI) Segmentation and Reassembly sublayer, SAR Transmitter Side: generates AAL1 packet from SC, CSI and 47 byte packets and sends it Receiver Side: - divides AAL1 packet into SC, CSI and 47byte packets

15. NETAAL1 General Configuration 4 x 2.048 Mbps PCM Bus 4 x 2.048 Mbps PCM Bus CPU Transmit Pointer RAM Receive Pointer RAM NETAAL1 Transmit Payload RAM Receive Payload RAM 10 Mbps ATMBus 10 Mbps ATM Bus

16. Transmit side of NETAAL1 Transmit PCM Bus CPU AAL1 Header Generator Transmit Dynamic Parameter Table Transmit Static Parameter Table Transmit Parametric Algorithm Transmit Payload Flag RAM Transmit SAR Scheduler Unit Transmit ATM Bus Interface address data Transmit ATM Bus Transmit Pointer RAM data address Transmit Payload RAM CS SAR

17. Transmit NETAAL1 CS PCM Frame (125 μs.) PCM Frame (125 μs.) Nth channel timeslot Nth channel timeslot time ... Transmit Pointer Table 30th bit of X.30/V.110 frame Pointer Group for M+1th X.30/V.110 frame (80 Pointers) ... ... Flag byte bit Mth X.30/V.110 Frame M+1th X.30/V.110 Frame Payload Location for the Nth channel on the Transmit Side (in Payload RAM) byte ATM Header AAL1 Header bit

18. Transmit NETAAL1 SAR N = N + 1 AAL1 Header Generator Payload Flag RAM SC RAM Nth Channel Payload Ready? address Payload Flag of Nth channel Transmit Payload RAM Transmit SAR Scheduler Unit Payload Ready data Prepare AAL1 Header of Nth Channel Send Payload of Nth Channel to ATM Bus Interface ATM Bus Interface SC = SC + 1 ATM Bus

19. Receive Look Up Table Receive Side of NETAAL1 CPU Receive Static Parameter Table Receive Parametric Algorithm Receive Dynamic Parameter Table Receive SNP/SN Analyzer Receive Payload Flag RAM address Receive ATM Bus Interface data Receive Pointer Table address data Receive Payload RAM Receive ATM Bus Receive PCM Bus SAR CS

20. Receive NETAAL1 SAR Receive Look Up Table AAL1 Header SNP Error Detection- Correction AAL1 Header SN Analyzer VPI VCI Nth address ATM Bus ATM Bus Interface ATM Cell Filter Receive Payload RAM Payload Flag of Nth Channel Receive Payload Flag RAM Payload Ready

21. Receive NETAAL1 CS PCM Frame (125 μs.) PCM Frame (125 μs.) Nth channel timeslot Nth channel timeslot time ... Receive Pointer Table 30th bit of X.30/V.110 frame Pointer Group for M+1th X.30/V.110 frame (80 Pointers) ... ... Flag byte bit Mth X.30/V.110 Frame M+1th X.30/V.110 Frame Payload Location for the Nth channel on the Receive Side (in Payload RAM) byte ATM Header AAL1 Header bit

22. Design Technology NETAAL1 implemented as a digital integrated circuit designed with Verilog Hardware Description Language (Verilog HDL) 100.000 lines of Verilog and C code in 5 months Flip-Flop Model always @(posedge clock) begin out_reg <= in_reg; end in_reg out_reg FF clock

23. Design Environment Statistics Static Timing Analysis is mandatory for this complexity Minimal CPU time statistics of postroute simulations for 4 cell transmission of the Transmit AAL1

24. Design Environment Statistics Parametric synthesis results of Transmit NETAAL1

25. Design Environment Statistics Placement&Routing statistics of Transmit NETAAL1: Sept 1st - 30th, 1999

26. Design Environment Statistics Parametric synthesis results of Receive NETAAL1

27. Design Environment Statistics Placement&Routing statistics of Receive NETAAL1: Sept 1st - 10th, 1999

28. Design Technology NETAAL1 has been implemented with Top-Down Design Flow in_reg out_reg always @(posedge clock) out_reg <= in_reg; clock Design Entry P&R chip Synthesis Verify Verify Verify Automated verification environment comparison

29. Internal monitors & cell file dumpers Design Technology open_aal1_connection (<chip>, <pcm>, <ts>, <vpi>, <vci>); CPU Simulation Model PCM Bus Simulation Model C Interfaces to external tools Testvector generators Macro Behavioral Model Generators Simulation mode check RAM Simulation Models RAM Simulation Models Transmit NETAAL1 Receive NETAAL1 Internal monitors & cell file dumpers ATM Bus Simulation Model Verilog and C based Automated Verification Environment

30. Design Technology NETAAL1 implemented in Field Programmable Gate Arrays (FPGA) of Xilinx transistor count ca. 1.000.000 Transmit NETAAL1 implemented in XC40150XV Receive NETAAL1 implemented in XC40150XV