RELIABILITY ISSUES IN ADVANCED CMOS TECHNOLOGIES: FROM ELECTRICAL STRESSES TO RADIATION DAMAGE

1. RELIABILITY ISSUES IN ADVANCED CMOS TECHNOLOGIES: FROM ELECTRICAL STRESSES TO RADIATION DAMAGE Alessandro Paccagnella DEI, Università di Padova, Padova, Italy e-mail: alessandro.paccagnella@unipd.it EWRHE, Villlard de Lans, 31 March 2004

2. Outline • Introduction • Floating Gate (FG) memories: Flash memories • SEE and data retention • TID and endurance • Stressing the gate oxides • Plasma damage • Final considerations

3. Introduction Reliability Electrical stresses Radiation stresses Electrical+radiation stresses

4. Floating Gate memories

5. Floating Gate memories overview • Electrons stored in the FG • VTH grows (CG) (FG) • Writing (Flash): • Channel Hot Electron tunnelling • Erasing (Flash): • Fowler-Nordheim tunnelling Tunnel Oxide Main reliability issues: - Endurance (W/R/E cycles) - Data retention

6. Endurance/1 • Decrease of the programming window as the number of P/E cycles increase • Accumulation of defects in the tunnel oxide

7. Endurance/2 • Increase of the writing time for increasing number of cycles

8. Data retention Log (bit) • After the burn-in (bake) test, one bit has lost charge and VT decreased

9. Rad effects: literature review • Test of off-the-shelf components: • No information on internal circuitry • No information on actual threshold voltage of cells (Direct Memory Access - DMA not available: only 0/1 outputs) • Many different failure modes: • Standby current exceeding limits • Stuck bits (cannot be reprogrammed) • Failing in writing/erasing • Functional interruption (Single Event Functional Interrupt, SEFI), etc. • Destructive events (Single Event Latchup, SEL), etc.

10. Literature review – TID/1 Time to erasure [s] • Nguyen, et al, IEEE Rad. Eff. Data Workshop, 1998 • Intel Flash, 2x8Mbit • Charge pump is the weak spot Total Dose [krad(SiO2)]

11. Literature review – TID/2 • Nguyen, et al, IEEE T-NS, 1999 • Intel StrataFlash, 64Mbit, 2 bits/cell • Irradiated in Write/Read/Erase mode • Unbiased device better than biased one  circuitry!

12. Literature review – SEE/1 • Schwartz et al, IEEE T-NS, 1997 • Several different failure modes

13. Literature review – SEE/2 Threshold LET Saturation cross section • Nguyen, et al, IEEE T-NS, 1999 • Cross section for buffer errors

14. Literature review – SEE/3 • Roth, et al, IEEE Rad. Eff. Data Workshop, 2000 • Toshiba 256 Mbit • Cross section for page buffer and address buffer errors • Different failures are possible! Alpha particle Silicon Nickel Iodine

15. Radiation effects on Floating Gate memories • Most of published studies: • Both SEE and TID tests • Failure happens in control systems (state machines, buffers, charge pump) • Stored information not directly accessible in commercial devices (no DMA available) • Recent results have shown that [1][2]: • Bit flips are not likely but may happen in FG arrays • The main charge loss is due to a transient mechanism [1] Cellere, et al., T-NS, Dec.2001 [2] Cellere, et al., T-NS, Dec.2002

16. DVTH spatial distribution After 2x107 Iodine ions/cm2 -DVTH • All cells programmed to “1” • Multiple Hits on a cell (~1.5% of hit cells) • Arrows: |DVTH|>2V • 3 bits with VTH<4V

17. Retention properties of Floating Gate memories • FG cells should ensure a data retention time of 10 yrs at room temperature: low leakage from FG • Accelerated electrical stresses are customarily performed in order to verify that Write/Erase electrical operations at high fields do not endanger the long time retention properties • Appearance of a single failing bit is a big concern: the memory chip fails • Data retention properties of irradiated FG cells: an open question

18. VTH statistical distribution/1 Fresh After 2x107 I ions /cm2 • 0.15mm2 FG devices • I ion irradiation • A secondary peak appears at ~6V • The very low VTH tail is probably due to double hits (1.5% of hit cells at this fluence)

19. On the charge loss mechanism DQ Fresh After 2•107 I ions /cm2 • DQ=3,500 electrons • I ion irradiation • 7,000 e/h pairs generated • 1% surviving recombination • 70 holes injected in FG • No known mechanism can explain these data!

20. VTH statistical distribution/2 Fresh After 2·106 cm-2 After 107 cm-2 After 2·107 cm-2 • 0.15mm2 FG devices • Si ion irradiation • Large statistical tails, linearly growing with fluence • Tail bits can result in read error

21. ID-VG characteristics of hit cells • EPROM, Ag irradiation • Hit cells exhibited a shift (but no clear deformation) of the ID-VG curve • FG charge loss is the only immediately detectable effect of irradiation (FG MOSFET is still working) …but is this effect the only one?

22. Radiation Effects on VTH distributions 0.04mm2 (small) devices • Large tails after irradiation • Number of bits in tail does not depend on ion LET (it depends on fluence) • DVTH strongly depends on ion LET • These cells (hit) only are considered in the next experiments

23. Data retention in hit FG cells - 1 After 20 days After 30 min After program 0.04mm2 (small) devices • Hit devices only were re-programmed 99.99% 93.4% 30.7% 4.8% Cumulative probability • After only 30min a clear tail appears… 0.67% 0.09% 0.012% • …which increases more and more with time 0.002% 3 4 5 6 7 8 V (V) TH After 20 days, DVTH~4V!!!

24. If the same experiment is repeated on large FG devices: same type of results, but smaller effect Strong dependence on FG area Data retention in hit FG cells - 2 0.15mm2 (large) devices

25. Modeling • In order to evaluate quantitatively the leakage current, an original model has been developed (Larcher et al., IEEE-TNS, 2003) • Modeling has been possible only by knowing in detail the cell structure and layout • Close collaboration with foundry is needed to develop quantitative models of complex devices

26. Data retention in hit FG cells: model • Why are devices with smaller FG area more sensitive? • Q  charge stored in the FG • CPPFG/CG capacitance • VTH after UV erasure (no excess charge FG) • If Itunnel is due to a small path (independent on FG area), charge loss over time increases if FG area decreases Charge loss is mediated by a localized conductive path through tunnel oxide

27. Model – 1 Ion track holes Tunnel Oxide electrons Floating gate (electrons stored) • Ion generates a plasma of electrons and holes • Part of these will recombine (99% for Iodine in our conditions)… Oxide defects • …generating some defect Substrate

28. Model – 2 Tunnel Oxide Floating gate (electrons stored) • ..while holes will take more time • Electrons will be quickly swept away… • During their motion, holes generate other defects Electron tunneling Finally, we obtain a number of defects (depending on ion LET) aligned along the ion track Substrate

29. Model - 3 Tunnel Oxide 8nm • Consider the ion track [1] Floating gate (electrons stored) • How can we evaluate the current along this path? • Randomly generate a Gaussian distribution of defects I=SIn • Evaluate the current through each possible path Substrate • Then sum all the currents [1] Oldham, T-NS, Dec.1985

30. Model – 4 • The whole procedure is repeated 10,000 times, to obtain (Monte Carlo approach): • Average value of the current • Statistical variations • The number of defects is used as a running parameter • Features: • Considers all possible percolation paths • Considers barrier deformation induced by positively charged traps • Couples electrons to oxide phonons • Calculates capture and emission rate of each trap, based on its energetic and physical position

31. Experimental data obtained from 0.04mm2 device irradiated with I previously shown Bars  variance (spread) of experimental data Lines  calculations Model vs. Experimental • With 20 defects, good agreement on: • Mean value • Extreme values (spread)

32. The model can be use to predict retention properties of device with thinner tunnel oxide This simulations done for EOX=1.8MV/cm Number of defects scaled accordingly to oxide thickness Scaling oxide thickness Gate leakage increases by more than one order of magnitude if TOX decreases by 30%

33. Cosiderations on FG cells/SEE • Large tails in cumulative probability plots of Flash device after irradiation with heavy ions • Hit cell (and only hit ones) show retention problems • A path of defects is generated by the impinging ion • Electrons can tunnel through these defects discharging the FG • Proposed a model to describe results, featuring statistical approach and phonon-assisted tunneling • Device with smaller FG area and thinner tunnel oxide are more sensitive (NAND-based?)

34. TID effects on FG cells • Tests on test structures with Co60 gamma rays • FG cells feature a selection MOSFET (2 MOSFETs per memory cell) • TID studies have been coupled to usual endurance stresses to evaluate the impact of ionizing radiation on the W/R/E characteristics

35. Charge loss from charged FG • Reduction of stored charge  change of FG VTH, moving toward the “intrinsic” VTH • Errors in array: • lower part of the “0” distribution approaches the 1.7V limit after 90krad (SiO2) • failures in the array are possible (even if not sure) after this dose has been exceeded

36. Basic models for charge loss from FG A) electron/ion interaction e- FG Ionizing radiation B) Holes trapped in tunnel oxide C) Holes injected in FG Tunnel Oxide Si-sub Interpoly (ONO) Oxide Snyder, et al, IEEE T-NS 1989

37. Modeling charge loss from FG/1 • Photoemission (direct interaction between stored electrons and radiation) • Neglected • Charge trapping in the oxide: • Neglected in modeling • (Relatively) thin oxides • Can be evaluated after irradiation and electrical stress In our model, the key role is played by charge generation and recombination in oxides

38. Modeling charge loss from FG/2 • Several contributions: • Gate oxide (Qtunnel) • “Bottom” SiO2 layer (QONO1) • Nitride layer (QONO2) • “Top” SiO2 layer (QONO2) QONO2 QONO1 Qtunnel

39. Floating Gate Modeling charge loss from FG/3 Substrate Si3N4 electrons holes Floating Gate • Charge generation by radiation: • 18eV per e/h pair (Benedetto et al, IEEE T-NS, 1986) • Recombination: • function of electric field • Evaluated based on existing data (Ausman, HDLR, 1986, Oldham, et al, IEEE T-NS, 1983) • Remaining e/h are injected in FG Qtunnel QONO1

40. Modeling charge loss from FG/4 Control Gate SiO2 Si3N4 SiO2 Floating Gate electrons holes QONO2 • Nitride layer: • No charge generation • 100% charge trapping • Why DVTH? • Charge injected in nitride from “top” and “bottom”  sheet charge layer  DVTH

41. Modeling charge loss from FG/5 • Qtunnel: generated in gate oxide • QONO1: generated in “bottom” SiO2 layer • QONO2: resulting from charge injection and trapping in nitride • Good agreement with experimental data • Underestimation at high doses: • Photoemission • Electric field decreases when FG loses electrons (or holes)  enhanced recombination • “Bottom” SiO2 layer is the key for device reliability

42. Interaction of electrical stress and irradiation • Electrical stress generates E’ centers • These are occupied by electrons generated by irradiation • Negative charge trapping • Electrical stress  irradiation (2.7 Mrad(SiO2))

43. FG leakage • No increase of the gate leakage current observed after 3 Mrad (red symbols) 100 P/E kcycles Leakage Current [a.u.] 20 P/E cycles 10 P/E kcycles 3 3,5 4 4,5 5 5,5 6 6,5 Electric Field [MV/cm]

44. Considerations on FG memories • Errors may take place in the FG array  • Less probable than errors in the control circuitry (higher doses required)  • More insidious: the event itself often cannot be immediately detected, but it can lead to: • Reduced noise margin  increased error rate  • Retention problems  • Designing a rad-hard control circuitry does not automatically qualify FG memories for harsh environments  • For TID and SEE: • Prompt effects • Long-term effects • Device scaling and design issues still open

45. Stressing the gate oxides

46. Assessing the gate oxide quality • Gate oxide Breakdown has been taken as the life time end marker for a long time, when a single breakdown mode was possible (tox>7 nm) • Different electrical tests are available to test the gate oxide quality and reliability in CMOS components, which is typically measured by looking at the statistical distributions of parameters such: • Breakdown field • Time-to-breakdown • …obtained through accelerated stresses at fields higher than during the device operation

47. Accelerated life tests: Electrical Stresses • Electrical Stresses: • Constant Current Stress (CCS) • Constant Voltage Stress (CVS) • Pulsed Voltage Stress (PVS) • Ramped Stresses Fresh characterization Electrical stress Post-stress characterization Device Under Test CCS CVS PVS

48. Gate oxide leakage currents SiO2 Anode Cathode Due to defect generation several leakage currents can appear in thin gate oxides after stress: Stress Induced leakage Current (SILC) Soft Breakdown (SB) Hard Breakdown (HB)

49. Problems associated to scaling Tox 10-6 HB 10-7 SB 10-8 Jg (A/cm²) 10-9 SILC 10-10 10-11 fresh 10-12 0 1 2 3 4 5 6 7 Vg (V) High electric fields applied to the gate oxide may produce anomalous gate leakage: • SILC (Stress Induced Leakage Current) • SB (Soft Breakdown) • HB (Hard Breakdown) What is the end-of-life marker? • MOSFET may survive SB [1] and SILC, not HB [1] B.E. Weir et al., IEDM 1997

50. SILC and SB vs. tox 10-5 10-6 4 nm 2.8 nm 2.8 nm 10-7 10-6 10-8 10-7 Jg [A/cm2] 10-9 Ig [A] 4 nm 10-8 5.2 nm 10-10 5.2 nm 10-9 10-11 SILC 10-10 SB Fresh 10-12 Fresh 10-11 10-13 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Vg [V] Vg [V] • SILC tends to become negligible in comparison with the pre-stress current as tox decreases • SB current is typically >> SILC • HB is unlikely in ultrathin oxides due to the low VDD