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MAKING A “MODEL”

MAKING A “MODEL”. BOB PEDDENPOHL MODELING MANAGER CYPRESS MODELING CENTER LEXINGTON, KY. OUTLINE. WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?. DESIGN KIT MAKES MONEY. DESIGN KIT MAKES MONEY. OUTLINE. WHAT DOES CY KENTUCKY DO?

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MAKING A “MODEL”

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  1. MAKING A “MODEL” BOB PEDDENPOHL MODELING MANAGER CYPRESS MODELING CENTER LEXINGTON, KY

  2. OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

  3. DESIGN KIT MAKES MONEY

  4. DESIGN KIT MAKES MONEY

  5. OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

  6. INTRODUCTION: MODELS • GENERIC DEFINITION • MAN MADE EXPRESSIONS TO REPRESENT MOTHER NATURE • VLSI DESIGN DEFINITION • MODELS = DESIGNERS PERCEPTION OF TECHNOLOGY • ENGINEERING DEFINITION • MODELS = PHYSICAL EQUATIONS + PARAMETERS Ids = BETA (Vgs-VT)^2 • where VT = 0.6 BETA = w/l*COX*MOBILITY = 1E-6

  7. ANALYTICAL (OR COMPACT) ANALYTICAL OR COMPACT DEVICE MODELS BASED PRIMARILY ON DEVICE PHYSICS. FITTING PARAMETERS INTRODUCED TO IMPROVE ACCURACY INTRODUCTION:TYPES OF MODELS SIMULATION MODELS TABLE LOOKUP NUMERICAL NUMERICAL SOLUTION OF DEVICE CHARACTERISTIC SIMULATORS ACCESS MEASURED DC/AC DATA IN A TABULAR FORM

  8. SCHEMATICS USE BSIM COMPACT MODELS

  9. INTRODUCTION: MODELS LIMITATIONS IDEAL VS REALITY IDEAL DESIGN SIMULATIONS EXACTLY EQUAL SILICON MEASUREMENTS REALITY MODEL NOT PERFECT MODEL HAS ACCURACY LIMITATIONS GOOD DESIGNER UNDERSTANDS MODEL LIMITATIONS NEED TO MODEL PROCESS VARIATIONS NEED MODELS QUICKLY TO ENABLE DESIGNERS

  10. OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

  11. WHAT MODELS USED AT UK? WHAT CY TECHNOLOGY DID YOU USE? RAM7: Wmin/Lmin = 0.42/0.20um, Vcc=1.8V, Idrive = 9.99 mA WHEN WAS TECHNOLOGY QUALIFIED? MODEL FROZEN Q302 WHAT TYPE OF MOSFETS? LV MOS (NSHORT/PSHORT), LVT PMOS (PLOWVT) CELL FETS (NPASS, NPD, PPU) WHAT’S NSHORT ELECTRICAL TOX? JUNCTION DEPTH? TOX= 41 A, XJ = 0.1um

  12. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  13. SELECT “GOLDEN” WAFER • IDEAL: MODELING SILICON CLOSE TO NOMINAL • REALITY: ~400+ PARAMETERS, ONLY MOST IMPORTANT ON TARGET NOMINAL MAX MIN WAFER

  14. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  15. MEASUREMENTS: HARDWARE & SOFTWARE

  16. MEASUREMENTS: COMPLETE MOS • FET DC (VTH0, RDSW) • FET AC (CGDO,DLC) • DIODE DC (JS,JSW) • DIODE AC (CJ, CJSW)

  17. MEASUREMENTS: FET DC

  18. MEASUREMENTS: FET DC • MODEL NEEDS SCALE WITHIN ALL GEOMETRY, TEMP

  19. MEASUREMENTS: DC FET QA, VTH VS. L • MODEL ACCURACY <=> MEASUREMENT ACCURACY • CONDENSED DATA TRENDS Strong Halo , L dependence Normal SCE Halo with SCE

  20. LOCOS (+k3) STI (-k3) MEASUREMENTS: DC FET QA, VTH VS. W • MODEL ACCURACY <=> MEASUREMENT ACCURACY • CONDENSED DATA TRENDS

  21. MEASUREMENTS: FET AC

  22. MEASUREMENTS: DIODE DC/AC REVERSE BIAS DC CHARACTERISTIC REVERSE BIAS AC CHAR.= f(CJA, CJP, EX,) I_FORWARD ~mA I_Reverse ~ pA

  23. O/P IN R10 C9 MEASUREMENTS: TRANSIENT • RING OSCILLATOR VALIDATION OF MODEL

  24. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  25. Short Channel Effects Drive Current Channel Length Modulation WAFER CASE: DC MOS EXTRACTION • MODEL = EQUATIONS + PARAMETERS • EQUATIONS (BSIM3V3) + MODEL PARAMETERS = WAFER CASE MODEL Mobility Model Threshold Model

  26. WAFER CASE: MOS MODEL BINNING Long/Wide Constant Vt Short Channel Effects (HALO/DIBL) Narrow Width Effects (STI/LOCOS)

  27. WAFER CASE: AC FET + DIODE • MODEL EXTRACTION • MODEL = EQUATIONS + PARAMETERS • EQUATIONS (BSIM3V3) + PARAMETERS (EXTRACTED FROM MEASUREMENTS) = MODEL (WAFER CASE) MOSFET CV MODEL Accumulation MOS DIODE IV MODEL Inversion BSIM3 Limitation Intrinsic Cap for Analog Design MOS DIODE CV MODEL

  28. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  29. O/P IN LAYOUT (DESIGN DEP.) LAYOUT MODEL: (ILD, METAL THICK) CALIBRE RCX CIRCUIT: FET DELAY + Rinterconnect + Cinterconnect SPICE MODELS RO SIMS = RO MEAS RO CAL: LAYOUT EXTRACTED SIMULATION • VALIDATE CAD EXTRACTION RULES + MOS BSIM MODELS R10 C9

  30. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  31. NOMINAL MAX MIN WAFER CORNER MODELS • WAFER CASE SIMULATIONS = WAFER MEASUREMENTS • WHAT ABOUT PROCESS VARIATIONS? • WILL MY DESIGN YIELD?

  32. NOMINAL MAX MIN tt.cor wafer.cor ss.cor ff.cor CORNER MODELS REALITY EVERY SITE/WAFER/LOT/SPLIT IS DIFFERENT ( PROCESS VARIATIONS) WORKING WITH REALITY CORNERS: MODELING SPACE TO COVER ALL POSSIBILITIES (STATISTICALLY) IN PROCESS TEAM EFFORT TO GET GOOD YIELD FAB: +/-4 SIGMA E-TEST  99.99% WAFERS INSIDE MIN/MAX MODELING: MIN/MAX MODELS MATCH FAB LIMITS DESIGN: SIMULATE DESIGN WORKING AT MIN/MAX LIMITS ALL 3 GROUPS WORKING = GOOD PRODUCT YIELD

  33. WHY 5 MOS CORNERS? • VTs AT SS & FF = 70% SPEC RANGE • VTs AT FS/SF = 100% SPEC RANGE fs ss sf ff tt tt ff sf ss fs VTXNS15 vs. VTXPS15 (V) (Vth @ W/L=25/0.15um) IDSNS15 vs. IDSPS15 (mA) Idrive (Vgs=Vds=Vcc) W/L=25/0.15um

  34. WHY CORNER METHODOLOGY IMPORTANT • MODEL MUST MATCH DESIGN/FAB AGREED LIMITS • FAB WANTS WIDE MIN/MAX LIMITS • STATISTICAL PROCESS CONTROL (SPC) • HOW GOOD DOES A PROCESS RUN WITHIN IT’S NOM/MIN/MAX • DESIGN WANTS NARROW MIN/MAX LIMITS • EASIER TO DESIGN • SMALL PROCESS VARIATION  SMALLER SI AREA

  35. MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

  36. QA: MODEL DOCUMENTATION • MODEL SUMMARY TABLE • MODEL ACCURACY IN SUB-THRESHOLD, GM ACCURACY

  37. APPENDIX BOB PEDDENPOHL (PED) CYPRESS MODELING CENTER

  38. Applying the Corner Models Design FET Corners tt, ff, ss, sf, fs CellFET Corners ttcell, ffcell, sscell Interconnects/Passives trtc, hrlc, lrhc Nmos/Pmos Nthick/Pthick (HV) Diode PNP Npass Nlatch Platch Interconnect R tres, fres, sres Interconnect C tpar, fpar, spar r+c.mod Temp coef of R metal/contact/poly/diff Sheet resistances C for various line/space

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