COMBINATIONAL LOGIC - 2

1. COMBINATIONAL LOGIC - 2

2. Sizing Logic Path for Speed

3. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic?

4. Buffer Example To find N: fi= Ci+1/Ci ~ 4

5. Buffer Example Generalisation In Out CL 1 2 N Rewrite delay in new form (in units of tinv) For inverter: pi = internal delay = 1 gi = gate to internal cap ratio = 1/  =1 for  =1 How to generalize this to any logic path?

6. Delay in Logic gates f = effective fanout (Cout/Cin) Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

7. Electrical Effort Estimates of intrinsic delay factors of various logic types assuming simple layout styles, and a fixed PMOS/NMOS ratio.

8. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

9. Logical Effort g = 5/3 g = 4/3 g = 1 Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current

10. Logical Effort of Gates

11. Logical Effort of Gates t pNAND g = p = d = t pINV Normalized delay (d) g = p = d = F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

12. Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)+2 t pINV Normalized delay (d) g = 1 p = 1 d = gf+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

13. Logical Effort of Gates

14. Add Branching Effort Branching effort:

15. Multistage Networks Stage effort: hi = gifi Path electrical effort: F = f1f2 … fn = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB (for inverter H = F) Path delay D = Sdi = Spi + Shi

16. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay

17. Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

18. Example: Optimize Path Effective fanout, F = G = H = h = a = b =

19. Example: Optimize Path Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/h = 2.59

20. Example – 8-input AND

21. Method of Logical Effort • Compute the path effort: H = GBF • Find the best number of stages N ~ log4H • Compute the stage effort h = H1/N • Sketch the path with this number of stages • Work either from either end, find sizes: Cin = Cout*g/h Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

22. Summary Replace F, f with H and h Replace H, h with F and f Sutherland, Sproull Harris

23. Ratioed Logic

24. Overview

25. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

26. Static CMOS

27. Alternatives to Static CMOS • Static CMOS is robust and reliable • l But • » Large (2N transistors) • » Slow (large capacitance) • l Hence … A quest for alternative logic • styles that are smaller, faster, or lower power.

28. Ratioed Logic

29. Ratioed Logic

30. Active Loads

31. Load Lines of Ratioed Gates

32. Pseudo-NMOS

33. Pseudo-NMOS VTC

34. Pseudo-NMOS Performance

35. Pseudo-NMOS NAND Gate VDD GND

36. Improved Loads (1)

37. Improved Loads (2) V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Differential Cascode Voltage Switch Logic (DCVSL)

38. DCVSL Example

39. DCVSL AND/NAND Gate

40. 2.5 1.5 0.5 -0.5 0 0.2 0.4 0.6 0.8 1.0 DCVSL NAND/AND Transient Response A B [V] e A B g a t l o A , B V A,B Time [ns]

41. Pass Transistor Logic

42. Pass-Transistor Logic

43. Complimentary Pass Transistor Logic

44. Complimentary Pass Transistor Logic (Example)

45. 4 Input NAND in CPL

46. NMOS-Only Logic 3.0 In Out 2.0 [V] x e g a t l o V 1.0 0.0 0 0.5 1 1.5 2 Time [ns]

47. NMOS-only Switch V C = 2.5 V C = 2.5 M 2 A = 2.5 V B A = 2.5 V M n B M C 1 L V does not pull up to 2.5V, but 2.5V - V TN B Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect)

48. Cascading Rules for PTL

49. Solution 1: NMOS Only Logic: Level Restoring Transistor • Advantage: Full Swing • Disadvantage: More Complex, Larger Capacitance • Careful sizing of Mr is requied

50. Level Restoring Transistor Size VX = VDD Rn/(Rr + Rn) < VM • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem