UFRGS

1. UFRGS Design of an Embedded System for the Proactive Maintenance of Electrical Valves Luiz F. Gonçalves, Jefferson L. Bosa, Renato V. B. Henriques, Marcelo S. Lubaszewski Natal, August 31st to September 3rd, 2009

2. OUTLINE • Introduction • Proactive maintenance • Fault detection and classification • Embedded system design • Conclusions

3. INTRODUCTION

4. INTRODUCTION • Recent advances in: • Electronics • Computing • Proactive ≠ corrective, preventive or predictive To automate and integrate proactive (also know as intelligent) maintenance tasks into embedded system Focuses on fault prediction and diagnosis based on component lifetimes and on system on-line monitoring That are based either on post-failure correction or on off-line periodic system checking

5. Proactive maintenance scheme Signal processing Statistical analysis Artificial intelligent MAINTENANCE Systems or equipments On-line monitoring Signals of vibration, temperature, torque, and others Quantify the performance degradation and determine the remaining system lifetime

6. Proactive maintenance scheme Wavelet packet transform Self-organizing maps (prototyped using FPGAs) PROACTIVE MAINTENANCE • Embedded system for the proactive maintenance Electrical valves Model Signals of torque and position Oil distribution network Quantify the degradation and diagnose the fault location

7. PROACTIVE MAINTENANCE

8. MAINTENANCE SCHEME • Proposed system for electrical actuators Mathematical model Self-organizing maps Wavelet packet transform

9. MATHEMATICAL MODEL • Electrical actuator Model Fault injection Main components Forces Differential and algebraic equations

10. SIGNAL PROCESSING • Wavelet packet transform • Preserves timing and spectral information • Suitable for the analysis of non-stationary signals • Capability of decomposing the signal in frequency bands • Energy (spectral density) • Torque • Position • The energy is used by the self-organizing maps Divided into N frequency bands The WPT runs in a PC station during the training plhase During on-line testing, the WPT shall be part of the embedded system

11. SELF-ORGANIZING MAPS (SOM) • SOM or Kohonen maps (class of neural networks) • Unsupervised learning paradigm based on: • Competition (searcher the winner neuron) • Cooperation (identifying the direct neighbors) • Adaptation (updating the synaptic weights) The goal of a SOM is after trained, mapping any input data from a Rn space representation into R2 lattice-like matrix Synaptic weight vector Energy vector

12. SELF-ORGANIZING MAPS • Competition step (Euclidean distance): • Using these equation, searches in the map the neuron with the weights (WBMU) that best matches the energy vector (E) • Thus, two maps are trained: • Fault detection: considering only typical situations of normal operation • Fault classification: considering normal, degraded and faulty situations • The misbehaviors are simulated by injecting parameter deviations into the valve mathematical model • For detection the min(Dkj), or the Quantization Error, is computed • For classification one map is colored based in the distance betwen W and E

13. FAULT DETECTION AND CLASSIFICATION

14. EXPERIMENTAL RESULTS • To train the fault detection map, a lot of simulations are performed to obtain typical values of torque and opening position under normal valve operation • To train the fault classification map, fault simulation is needed, some parameters are gradually incremented 100 operation cycles KR simulate the degradation of the internal valve worm gear, till it breaks KM deviations simulate the elasticity loss of the valve spring along time

15. MODEL RESULTS • Fault simulation Torque Position

16. DETECTION RESULTS • Fault detection Degradation Fault Fault free Faulty KR Faulty KM

17. CLASSIFICATION RESULTS • Fault classification map of faults in KR and KM Each cluster is assigned a different color During the on-line testing phase, a winner neuron computed for a measured input vector can be easily located in this map

18. EMBEDDED SYSTEM DESIGN

19. EMBEDDED SYSTEM DESIGN • For the on-line monitoring, the computation of the input vector WPT, winner neuron and quantization error, shall be embedded into the valve • These functions was implement using an FPGA platform (XUP Virtex2 PRO Xilinx) • The WPT computation runs in a Microblaze processor synthesized for the FPGA device (runs at a 100MHz) Virtex2 PRO

20. ARCHITECTURES • Parallel • higher consumption of area • Series • greater consumption of time The area is limited Time is not so important

21. OTHER SOLUTIONS 1. Takeshi Yamakawa, Keiichi Horio and Tomokazy Hiratsuka. Advanced Self-Organizing Maps Using Binary Weight Vector and Its Digital Hardware Design. 9th International Conference on Neural Information Processing, v.3, 2002. They proposed a new learning algorithm of the SOM (using Hamming distance and parallel processing) is proposed (processing time = 0.02s)

22. OTHER SOLUTIONS 2. Paolo Ienne, Patrick Thiran and Nikolaos Vassilas. Modified Self-Organizing Feature Map Algorithms for Efficient Digital Hardware Implementation. IEEE Transactions on Neural Networks, v.8, n.8, 1997. They describes three variants (parallel and series) of the SOM algorithm (update the weights after presentation of a group, or all, of input vectors)

23. OTHER SOLUTIONS 3. Pino, B., Pelayo, F. J., Ortega, J. and Prieto, A. Design and Evaluation of a Reconfigurable Digital Architecture for Self-Organizing Maps. 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, Granada, p.395–402, Apr.,1999. They presents a modular and reconfigurable digital architecture for SOM algorithm (using Manhattan distance)

24. ALGORITHM for k=1 to K / (input vector numbers) for j=1 to J / (neuron numbers) C1=C2=C3=0 for n=1 to N / (element numbers by vector) C1 = Enk - Mnj C2 = C1 * C1 C3 = C3 + C2 end Dkj = √ C3 / (vector of J lines) end [value , position] = min(Dkj) end Min (Dkj) MBMU

25. ARCHITECTURE • IP-core architecture proposed for the computation of WBMU e min Dkj and the hardware used to obtain Dkj : The operator of the Euclidean distance circuity shall be based on a floating point representation (IEEE 754) Most important and most area consuming block in the FPGA is the memory (BRAM)

26. AREA EVALUATION • Experiments performed with this system have show that map sizes of 90 neurons, with synaptic weight vectors of 20 elements of 32 bits each, are quite to reach the accuracy required FPGA area evaluation

27. PERFORMANCE EVALUATION • The gate valve takes 100s to travel the full range, from the closed to the 100% open position • The whole travel is performed in 20 incremental steps, lasting 5s each • WBMU and min Dkj computation time for a single (Th, a) measurement: In this application, t=5s is the time limit for all computations

28. CONCLUSIONS

29. CONCLUSIONS • Proactive maintenance scheme is proposed for the detection and diagnosis of faults in electrical valves, used for flow control in an oil distribution network • This is the first attempt to apply a proactive maintenance methodology to this sort of actuators • A hardware implementation of self-organizing maps is proposed to solve the valve maintenance problem • An embedded system implements these maps for the detection and classification of faults The maps are trained using a mathematical model (fault injection) The embedded system computes the best matching between an acquired measure and the neurons of the map

30. CONCLUSIONS • The embedded system was prototyped using an XUP Virtex2 PRO Xilinx FPGA Development Board • The results obtained for memory, requirements, area and performance point out to a low cost, promising solution for embedding maintenance in valves • Acknowledgements • CNPq • CAPES • Petrobrás

31. Thank you! luizfg@ece.ufrgs.br