1 / 65

Warp-Aware Trace Scheduling for GPUS

Warp-Aware Trace Scheduling for GPUS. James Jablin (Brown) Thomas Jablin (UIUC) Onur Mutlu (CMU) Maurice Herlihy (Brown). Historical Trends in GFLOPS: CPUs vs. GPUs. Reproduced from NVIDIA C Programming Guide (Version 5.0). Performance Pitfalls.

chidi
Download Presentation

Warp-Aware Trace Scheduling for GPUS

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Warp-Aware TraceScheduling for GPUS James Jablin (Brown) Thomas Jablin (UIUC) OnurMutlu (CMU) Maurice Herlihy (Brown)

  2. Historical Trends in GFLOPS:CPUs vs. GPUs Reproduced from NVIDIA C Programming Guide (Version 5.0)

  3. Performance Pitfalls Control flow can negatively affect performance.

  4. Performance Pitfalls Pipeline Stall – execution delay in an instruction pipeline to resolve a dependency

  5. Hardware: CPU versus GPU Reproduced from NVIDIA C Programming Guide (Version 5.0)

  6. Performance Pitfalls Pipeline Stall – execution delay in an instruction pipeline to resolve a dependency

  7. Performance Pitfalls Pipeline Stall – execution delay in an instruction pipeline to resolve a dependency Warp Divergence – threads within a warp take different paths and the different execution paths are serialized

  8. Warp Divergence Example

  9. Warp Divergence Example

  10. Warp Divergence Example

  11. Warp Divergence Example

  12. Warp Divergence Example

  13. Warp Divergence Example

  14. Warp Divergence Example

  15. Warp Divergence Example

  16. Warp-Aware Trace Scheduling Schedule instructions across basic block boundaries to expose additional ILP…

  17. Warp-Aware Trace Scheduling Schedule instructions across basic block boundaries to expose additional ILP… while managing and optimizing warp divergence.

  18. Origins: Microcode Trace Scheduling …generalizing local and disparate vertical-to-horizontal microcode compaction

  19. Origins: Microcode Trace Scheduling …generalizing local and disparate vertical-to-horizontal microcode compaction

  20. Origins: Microcode Trace Scheduling …generalizing local and disparate vertical-to-horizontal microcode compaction

  21. Origins: Microcode Trace Scheduling …generalizing local and disparate vertical-to-horizontal microcode compaction

  22. Origins: Microcode Trace Scheduling …generalizing local and disparate vertical-to-horizontal microcode compaction

More Related