1 / 33

L38: Viterbi Decoder 저전력 설계

L38: Viterbi Decoder 저전력 설계 . 성균관대학교 전기전자 및 컴퓨터공학부 조 준 동. Viterbi Decoder. Convolutional Encoder K = 3 (Constraint Length) R = 1/2 (Rate) . Viterbi Decoder. Information sequence : U = (0,0,1,0,1,0,...) Output codeword : V = (00,00,11,10,00,10,...) . Viterbi Decoder.

cicada
Download Presentation

L38: Viterbi Decoder 저전력 설계

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. L38: Viterbi Decoder저전력 설계 • 성균관대학교 • 전기전자 및 컴퓨터공학부 • 조 준 동 SungKyunKwan Univ.

  2. Viterbi Decoder • Convolutional Encoder • K = 3 (Constraint Length) • R = 1/2 (Rate) SungKyunKwan Univ.

  3. Viterbi Decoder • Information sequence : U = (0,0,1,0,1,0,...) • Output codeword : V = (00,00,11,10,00,10,...) SungKyunKwan Univ.

  4. Viterbi Decoder • Viterbi Decoder SungKyunKwan Univ.

  5. Viterbi Decoder • Branch Metric Unit(BMU) : The branch metrics measure the difference the received symbol and the symbol that causes the transitions between states in the trellis. • Add-Compare-Select Unit(ACSU) : To find the survivor path entering each state, the branch metric of a given transition is added to its corresponding partial path metric(PM) stored in the path metric memory (PMM). This new partial path metric is compared with all the other new partial metric corresponding to all the other transitions entering that state. The transition that has the minimum partial path metric is chosen to be the survivor path of the state. The path metric of the survivor path of each state is updated and stored back into the PMM. • Survivor memory Unit(SMU) : The survivor path are stored in the SMU. A traceback mechanism is applied on the SMU during the decoding stage to output the decoded data. SungKyunKwan Univ.

  6. Viterbi Decoder • Low power ACSU VLSI architecture • Conventional ACSU VLSI architecture • Butterfly structure SungKyunKwan Univ.

  7. Viterbi Decoder • Architecture of conventional ACSU SungKyunKwan Univ.

  8. Viterbi Decoder [SKKU. Solution] • Algorithm • The area and power of the lower power ACSU design are reduced by 20% and 30%, respectively, comparing with the conventional ACSU design SungKyunKwan Univ.

  9. Viterbi Decoder [SKKU. Solution] • Low power ACSU VLSI architecture [C-Y Tsui, ISLPED’99] SungKyunKwan Univ.

  10. Viterbi Decoder [SKKU. Solution] • Glitch minimization [Raghunathan, DAC’96] • (a) Lower power ACSU architecture (b) Conventional ACSU architecture • The power consumption of architecture (a) is larger than that of architecture (b) by more than 17% because of glitch power dissipation SungKyunKwan Univ.

  11. Viterbi Decoder [SKKU. Solution] • Glitches in control logic SungKyunKwan Univ.

  12. Viterbi Decoder • Low power traceback VLSI architecture • Systolic Viterbi, traceback decoder[J. Sparso’91] SungKyunKwan Univ.

  13. Viterbi Decoder • Received codeword : V = (00,00,11,10,00,10,...) SungKyunKwan Univ.

  14. Viterbi Decoder SungKyunKwan Univ.

  15. Viterbi Decoder SungKyunKwan Univ.

  16. Viterbi Decoder SungKyunKwan Univ.

  17. Viterbi Decoder • Systolic array decoder의 문제점 • The systolic array viterbi decoder is organized to input the decision vector and the smallest path metric out of the ACSU and to output the decode bit by shifting every register for every cycle. • This system consumes a great dynamic power consumption due to switching activities of registers which is almost 80% of the total power consumption because every data in TBU shifts for every cycle. SungKyunKwan Univ.

  18. Viterbi Decoder [SKKU. Solution] • Our low power trace-back unit SungKyunKwan Univ.

  19. Viterbi Decoder [SKKU. Solution] SungKyunKwan Univ.

  20. Viterbi Decoder [SKKU. Solution] SungKyunKwan Univ.

  21. Viterbi Decoder [SKKU. Solution] • After decision vector and the smallest path metric generated from ACSU are transferred to the Control Block (CB), the CB outputs the decision vector and the smallest path metric with the right cycle using a counter and a multiplexer. • The register array, which stores the value of trace-back from the CB, was provided to finally output decoded bit, not by shifting all higher 4-bit decision vector as in the classical TBU, but by shifting the lower 2-bit only, which is thesmallest path metric, to the left SungKyunKwan Univ.

  22. Viterbi Decoder [SKKU. Solution] • Experimental Result (area 11% , power 40% ) SungKyunKwan Univ.

  23. Viterbi Decoder [Stanford Solution] • Low Power Asynchronous Viterbi Decoder[Y.h.Lee , Stanford] • Algorithm SungKyunKwan Univ.

  24. Viterbi Decoder [Stanford Solution] • 초기화: 구속장의 5배의 trellis를 traceback하고, 그 경로를 저장한다. • Loop A. 추적과 비교 : 임의의 초기 스테이트를 선택해 trace back을 시작 한다. 동시에, route를 추적해 나가면서 각 node에서 저장된 route와 비교한다. B. 비교 값이 같으면 추적을 멈추고 저장된 route를 버린다. 같지 않 을 때는 A 과정을 반복한다. • 각각의 입력 신호에 대해 ② 과정을 반복한다. SungKyunKwan Univ.

  25. Viterbi Decoder [Stanford Solution] • Implementation • Self-timed TBU block diagram SungKyunKwan Univ.

  26. Viterbi Decoder • Self-timed TBU가 request 신호를 기다리는 동안 전력 소모가 없다. • ACS는 스테이트 결정 데이터를 버리기 위해 request 신호를 내보낸 다. • TBU는 이전의 surviving path memory와 previous path memory를 읽어 들여 비 교한다. • 같지 않으면, TBU는 previous path memory를 update하고 self- precharging, self-requesting을 한 다음 ③ 과정을 반복한다. 같으면, ⑤과정으로 간다. • TBU는 ACS에 scknowledgement 신호를 보내고, 다음 ACS의 request 신호를 위해 self-precharge한다. SungKyunKwan Univ.

  27. Low-Power Bit-Serial Viterbi DecoderH. Suzuki, Y. N. Chang, K. K. Parhi “Low-Power Bit-Serial Viterbi Decoder for 3rd Generation W-CDMA System”, 1999, CICC • Abstract • This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate =1/3 and the constraint length K=9(256 states) • The Add-Compare-Select(ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. • The chip was implemented using 0.5m CMOS technology and is operative at 20Mbps under 3.3V and 2Mbps under 1.8V. The power dissipation is only 9.8mW at 2Mbps operation under 1.8V SungKyunKwan Univ.

  28. Low-Power Bit-Serial Viterbi Decoder • Architecture Overview • 256 bit-serial ACS units are placed in parallel and each ACS unit include state metrics storage • Trace-back block, a 256 x 48 bit memory is required for the survivor path length of 48 SungKyunKwan Univ.

  29. Low-Power Bit-Serial Viterbi Decoder • Bit-Serial Viterbi Decoder Chip Diagram SungKyunKwan Univ.

  30. Low-Power Bit-Serial Viterbi Decoder • Bit-Serial ACS Unit • Bit-serial ACS unit SungKyunKwan Univ.

  31. Low-Power Bit-Serial Viterbi Decoder • Each ACS unit has three full-adders. • Two of them are used to add the state metric and the branch metric and the third one is used to compare two new state metrics • Reducing the overhead down to 17% of the whole area of the ACS unit SungKyunKwan Univ.

  32. Low-Power Bit-Serial Viterbi Decoder • Trace Back Strategy • Trace Back operation SungKyunKwan Univ.

  33. Low-Power Bit-Serial Viterbi Decoder • The memory size required in this paper is twice as large as the minimum memory size(256 x 2). • After 48 “TRACE BACK” operations, 24 decoded bits are obtained consecutively. • Two separate pointers, namely, a read pointer and a write pointer are required and the speed of the read pointer should be three times as fast as that of the write pointer • This operation was implemented with single-port memories using a time-multiplexed access method. SungKyunKwan Univ.

More Related