Designing Complex CMOS Gates: Techniques and Considerations

1. Chapter 6 Designing CombinationalLogic Circuits V1.0 4/25/2003

2. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In

3. Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either via a low-resistive path. V or V DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects duringswitching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

4. Static Complementary CMOS VDD In1 PMOS only (good for transfer 1) In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only (good for transfer 0) InN PUN and PDN are dual logic networks

5. CL CL CL CL Threshold Drops in NMOS and PMOS VDD VDD PUN S D VDD D S 0 VDD 0 VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD S D

6. Complementary CMOS Logic Style

7. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

8. PMOS Transistors in Series/Parallel Connection

9. Example Gate: NAND

10. Example Gate: NOR

11. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

12. Constructing a Complex Gate

13. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or GND in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No steady-state direct path between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

14. Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B A B A A Cint Switch Delay Model Req A A NOR2 INV NAND2

15. Rp Rp B A Cint CL Rn A Input Pattern Effects on Delay • Delay is dependent on the pattern of inputs • Low-to-high transition • Both inputs go low • Delay is 0.69 (Rp/2) CL • One input goes low • Delay is 0.69 (Rp) CL • High-to-low transition? • Both inputs go high (required for NAND) • Delay is 0.69 (2Rn)CL Rn B

16. Delay Dependence on Input Patterns A=B=10 A=10, B=1 Voltage [V] A=1, B=10 time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF A=1, B=10 (for both Cint and CL)

17. Rp Rp 2 2 Rp Rp A B B A Rn Cint Cint CL CL Rn Rn Rn B A A B 1 1 Transistor Sizing Assumes Rp = 2Rn at same W/L 4 4 2 2 NAND is preferred than NOR implementation!!

18. A D Transistor Sizing a Complex CMOS Gate B 8 4 C 8 4 OUT = D + A • (B + C) A 2 D 1 B 2 C 2

19. Fan-In Considerations 4-input NAND Gate

20. A B D C B A C3 C2 C1 CL C D Fan-In Considerations Distributed RC model (Elmore delay) tpHL = 0.69(R1C1+(R1+R2)C2 + (R1+R2+R3)C3 + (R1+R2+R3+R4)CL =0.69 Reqn(C1+2C2+3C3+4CL) Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case.

21. quadratic tpHL tp linear tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH fan-in

22. (tpHL, tpLH) as a Function of Fan-Out

23. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL

24. C3 C2 C1 CL Fast Complex Gates: Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing • Distributed RC line: • M1 > M2 > M3 > … > MN • (the FET closest to the • output is the smallest) • Not simple in Layout InN MN In3 M3 In2 M2 In1 M1

25. C2 C1 C1 C2 CL CL Fast Complex Gates: Design Technique 2 • Transistor ordering: Put late arrival signal near the output node. critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 Delay determined by time to discharge CL, C1 and C2 Delay determined by time to discharge CL

26. Fast Complex Gates:Design Technique 3 • Alternative logic structures (A) F =NAND8, C > B > A in speed (C) (B)

27. CL CL Fast Complex Gates:Design Technique 4 • Isolating fan-in from fan-out using buffer insertion

28. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic?

29. Buffer Example In Out CL 1 2 N (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path?

30. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

31. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1

32. Logical Effort From Sutherland, Sproull

33. Estimated Intrinsic Delay Factor

34. Logical Effort p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

35. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

36. Logical Effort of Gates

37. Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)f+2 t pINV Normalized delay (d) g = 1 p = 1 d = f+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (f)

38. Add Branching Effort Branching effort:

39. Multistage Networks • Stage effort: hi = gifi • Path electrical effort: F = Cout/Cin • Path logical effort: G = g1g2…gN • Branching effort: B = b1b2…bN • Path effort: H = GFB • Path delay D = Sdi = Spi + Shi

40. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay

41. Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

42. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = 5 G = 25/9 H = GF=125/9 = 13.9 h = 1.93 (optimal stage effort) = a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59

43. Example – 8-input AND

44. Method of Logical Effort • Compute the path effort: F = GBH • Find the best number of stages N ~ log4F • Compute the stage effort f = F1/N • Sketch the path with this number of stages • Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

45. Summary Sutherland, Sproull Harris

46. Pass-TransistorLogic

47. Pass-Transistor Logic

48. Example: AND Gate A, B: One is Input signal, the other is Control Signal

49. NMOS-Only Logic 3.0 In Out 2.0 [V] x e g a t l o V 1.0 0.0 0 0.5 1 1.5 2 Time [ns]

50. NMOS-only Switch V C = 2.5 V C = 2.5 M 2 A = 2.5 V B A = 2.5 V M n B M C 1 L V does not pull up to 2.5V, but 2.5V - V TN B Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect)