A2T: automatic abstraction from RTL to TLM IPs

1. A2T: automatic abstraction from RTL to TLM IPs

2. Outline • HIFSuite overview • Motivation for abstraction • Abstraction techniques • Tool features • Tested benchmarks

3. HIFSuite overview

4. HIFSuite overview A2T: RTL to TLM abstractiontool

5. Why automatic abstraction? CPU (Application + Drivers) MEM (TLM) Bus (TLM) TLM design Transactor IP core (RTL) RTL IP reuse IP core (RTL)

6. Why automatic abstraction? CPU (Application + Drivers) MEM (TLM) Bus (TLM) TLM design Transactor IP core (RTL) • RTL simulation is slow • is the transactor correct ? RTL IP reuse IP core (RTL)

7. Why automatic abstraction? CPU (Application + Drivers) • Fast simulation • Correct by construction • OSCI TLM 2.0 compliant • Untimed/Loosely Timed • -) Quantum Keeper (QK) • -) Delay Time (DT) • DT=0 if Untimed • Approximately Timed • -) Delay Time (DT) • -) 2-4 phases MEM (TLM) Bus (TLM) IP core (TLM) TLM design RTL /IP abstraction IP core (RTL)

8. Abstraction steps • RTL HDL (i.e., VHDL, Verilog, SystemC) to RTL hardware intermediate format (HIF) • Front-end conversion tool • RTL HIF to TLM HIF • A2T: merge of states, clock abstraction • TLM HIF to SystemC TLM • Back-end conversion tool

9. 1. Front-end/Back-end conversion tool Verilog SystemC TLM VHDL • Issues: • Different HDL semantics

10. 1. Front-end/Back end conversion tool (contd) Verilog SystemC HIF (TLM) HIF (RTL) VHDL • HIF has a proper semantics • HIF RTL (close to VHDL semantics) + HIF TLM • Front-end tool maps any HDL-related construct into HIF constructs

11. Framework for conversion verification • HIFSuite Regression Suite (HRS) • HRS consists of two environments: • From VHDL or Verilog to VHDL or Verilog • Synopsys Formality equivalence checking • From VHDL or Verilog to SystemC (and viceversa) • Dynamic simulation via Mentor Modelsim + EDALab ATPG (Ulisse)

12. x=24 β C Off x>=24 dx/dt= -Kx On x<=25 dx/dt= K(h-x) D A Entry S Exit α, T B Formal Framework: UNIVERCM α p_count: process (clk) begin ContaByte <= '0’; if Step = ‘1 then ContaByte <= ‘1’; end if; end process; F E x=25 Pure SW generation Software HIFSuite UNIVERCM Efficient simulation SystemC SystemC AMS SystemC TLM • Unique formalism for heterogeneous components • Handle discrete and continuous behaviors • Supports hardware and software descriptions • Non determinism versus determinism • Allows elaboration of intermediate models for • Software generation • Efficient system simulation

13. HIFSuite conversion tool limitations • Supported HDL constructs: • Almost all VHDL, Verilog and SystemC synthesizable constructs supported • Ongoing work for complete support • Documentation available on current supported constructs • Synthesizable constructs used in a non-synthesizable way supported! (e.g., while (x>0)) • TLM constructs supported only by the back-end conversion tool • they are generated in HIF during abstraction

14. 2. From RTL HIF to TLM HIF: A2T • Toolfeatures: • Merge of states and clock abstraction • RTL communication protocol abstraction • Cycle accurate to transaction accurate behavior abstraction • Data type abstraction • Correct-by-construction TLM IPs • event-based equivalence • OSCI TLM-2.0 compliant interfaces • 10x to 100x speedup depending on • RTL IP structure and target TLM protocol

15. clk uf1; 2.1 Merge of states and clk abstraction RTL TLM clk & ef0 ef0 A B A’ uf0; uf1; uf0; ef0 clk & ef0 clk & ef1 uf0; while (~ ef1) { uf2 }; uf1; A B A’ uf1; uf0; clk & ~ef1 uf2;

16. clk & ~ef1 uf2; 2.1 Merge of states and clk abstraction TLM ef0 RTL uf0; if (ef1) { uf1; // recursively, all the code representing the path of state B } else { uf2; // recursively, all the code representing the path of state C }; A’ B clk & ef1 clk & ef0 uf1; A uf0; C 16

17. 2.2 RTL comm. protocol abstraction RTL TLM // write #1 port_data data1; port_data_en  true; wait(); // write #2 port_data  data2; port_data_en  true; wait(); // write #2 result_en  port_result_en; while ( !result_en) wait(); result  port_result; … // writetransaction payload.command write; payload.data  data1; b_transport(payload, t); // writetransaction payload.data  data2; b_transport(payload, t); // readtransaction payload.command  read; b_transport(payload, t); result payload.result; …

18. result_OUT.write()<=result data1<=data_IN.read() data2<=data_IN.read() 2.3 CA to transaction accurate behavior clk data_IN read() data_en_IN result_OUT write() result_en_OUT Cycle- accurate (CA): • RTL-TLM event-basedequivalence: • Bombieriet al. [ACM/IEEE MEMOCODE 2006, 2007]; • Bombieriet al. [IEEE Transactions on Computer, 2010] write_transaction ( read(data1) ) read_transaction ( write(result) ) Transaction-accurate (TA): write_transaction ( read(data2) ) start transaction end transaction

19. 2.4 Data type abstraction HIF Suite Abstracted Data Types (HADT) Library (C++) IP core (TLM) HDL Data Types Library IP core (RTL) RTL /IP abstraction Data type abstraction HIFSuite HADT library: • Faster and more efficiente implementation • Logic and bit accurate types abstracted • Two versions: • Multivalue logic abstracted into 2-values logic • Multivalue logic mantained

20. 2.5 OSCI TLM-2.0 compliant interfaces • Different TLM IP interfaces can be generated during abstraction • Functionality code separated from protocol code • TLM 2.0 interfaces currently available: • Untimed/Loosely Timed • -) Quantum Keeper (QK)? • -) Delay Time (DT) • DT=0 if Untimed • Approximately Timed • -) Delay Time (DT) • -) 2-4 phases • Easily extendible

21. 2.6 Speedup: tested benchmarks • Div, Dist, Root VHDL/SystemC-RTL • Face Recognition System by STMicroelectronics • ECC, CRC VHDL/SystemC-RTL • VERTIGO project Platform by STMicroelectronics • BxxVHDL/Verilog • ITC-99 suite • ADPCM SystemC-RTL • Opencore • FFT VHDL • Magali Platform by CEA-Leti • I2C VHDL • COMPLEX project platform by STMicroelectronics

22. 2.6 Speedup: times

23. The tool

24. Thank you for further information please contact us: hifsuite@edalab.it http://hifsuite.edalab.it