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ADV784x EDID FEATURE OVERVIEW

ADV784x EDID FEATURE OVERVIEW. What is an EDID? (VGA or HDMI). Describes the capabilities of the sink Video resolution Color Spaces Maximum Pixel Clock Frequency Audio Format (PCM, DSD, DST, HBR) (HDMI Only) Audio Sampling Frequency (HDMI Only) Maximum Pixel Clock Frequency

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ADV784x EDID FEATURE OVERVIEW

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  1. ADV784x EDID FEATUREOVERVIEW

  2. What is an EDID? (VGA or HDMI) • Describes the capabilities of the sink • Video resolution • Color Spaces • Maximum Pixel Clock Frequency • Audio Format (PCM, DSD, DST, HBR) (HDMI Only) • Audio Sampling Frequency (HDMI Only) • Maximum Pixel Clock Frequency • EDID is generally stored in an external storage device • EDID storage device connected to the following • DDC port for HDMI • SCL/SDA signals on VGA connector • EDID size for VGA application • 128 bytes (typical VGA EDID size)

  3. EDID On HDMI Link SINK SOURCE HDMI link TMDS clock, data HPD 5V CEC DDC E-EDID

  4. E-EDID On VGA link SINK SOURCE SOURCE VGA Cable R, G, B channels HS, VS signals 5V (Pin 9) SCL (Pin 15) SDA (Pin12) E-EDID

  5. ADV7844/2 Internal E-EDID Features • Up to 512 bytes of shared data for all HDMI/VGA Ports • 2 shared segments • Two configurations are available • Supports a single EDID up to 512 bytes HDMI EDID • Supports two 256 byte EDIDs • Upper segment is for VGA EDID Information (up to 256 bytes) • Lower segment is HDMI EDID Information ( 256bytes) • EDID data stored in an external 512 byte SPI EEPROM • 2K or 4K are external SPI EEPROMs are supported • Segment pointer supported for large EDID (HDMI Only) • Required for EDID data bigger than 256 bytes

  6. HDMI EDID Data Structure EDID 1.3 128 bytes Block 1 – Segment 0 Mandatory Map Block 128 bytes Block 2 – Segment 0 Mandatory CEA Extensions ver. 3 128 bytes Block 3 - Segment 1 CEA Extensions ver. 3 128 bytes Block 3 - Segment 1 CEA Extensions ver. 3 128 bytes Block 3 - Segment 1 CEA Extensions ver. 3 128 bytes Block 3 - Segment 1 CEA Extensions ver. 3 128 bytes Block 4 - Segment 1 Optional

  7. VGA E-EDID Data Structure VGA EDID 1.3 128 bytes Block 1 – Segment 0 Mandatory EDID Extension (optional) 128 bytes Block 2 - Segment 0 Optional

  8. Internal EDID Controller • EDID Controller • The EDID controller handles all I2C requests from the DDC and the I2C ports • DVDD is the supply for the EDID Controller • Internal clock oscillator generates clock for the EDID controller. • This allows the EDID controller to be active in power down mode • Power On reset • A power on reset circuitry generates a reset to the EDID controller when DVDD is applied • The EDID controller can also be reset through I2C HDCP_REPT_EDID_RESET control.

  9. VGA / HDMI External connections VGA Port ADV7844/2 +5V SPI EEPROM 512byte(4kbit) 4 +5V (TV supply) SPI interface +3.3V +5V DVDDIO TVDD LDO HDMI Port A DVDD CVDD PVDD AVDD +1.8V LDO +5V HDMI Port B 10K +2.5V LDO DVDDIO_SDRAM +5V HDMI Port C +5V HDMI Port D PWRDNB RXD_5V_DET RXC_5V_DET RXB_5V_DET RXA_5V_DET

  10. Power Supply • +5V power supply from HDMI connector • Each HDMI connector can source up to 50mA • Current only flows from +5V signal toward the part • Each supply on the ADV7844/2 must be supplied power when reading internal EDID even in power down state • Main power supply • Source all current when available • Current always flows from main supply toward the part • PMOSFET Transistor • Transistor is non conducting when the main supply is present • Current is drawn from the HDMI connector in power down mode

  11. SPI Interface • Clock speed is ~3MHz • The CPU reads the EEPROM when the supply is available • In power down mode • Normal power mode • 2kb or 4kb EEPROMs supported from the following vendors • ATMEL • Thomson • Microchip • EP_MISO has an internal pull-down • If not required - all pins can be left unconnected

  12. Reading from/Writing to the SPI EEPROM • Reading from SPI EEPROM • The CPU reloads the data from the SPI EEPROM to the internal EDID RAM • On reset (if powerdown pin is set low) EDID power-down mode • When the self clearing bit LOAD_EDID is set • Storing data to SPI EEPROM • In-system-programming of the SPI EEPROM • The internal CPU program the external SPI EEPROM with data from the internal EDID RAM • Steps • Program the EDID RAM through the main I2C port • Load the data from the EDID RAM into SPI EEPROM with bit STORE_EDID

  13. Supporting EDID in Powerdown Chassis supply removed • When powering the ADV784x from the cable the following requirements need to be met. • Power should be supplied to each of the supplies and the PSS sequence should be adhered to. • In order to ensure that the ADV784x goes into power down mode correctly the following condition must be met. • When entering power down mode, the RESET pin should go low at /or before the PWRDNB pin. • This ensures that the part is fully reset/powered down as EDID power down mode is enabled. • Not adhering to above recommendation will cause the ADV784x to drawn more current than the 50mA HDMI Specification.

  14. ADV784x EDID CircuitryChassis supply removed • Circuitry to ensure that Reset and PWRDNB are pulled low at the same time.

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