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Lecture’s Overview

CMSC 411-101 Computer Architecture Lecture 8 Hardware Design Languages February 21, 2001 www.csee.umbc.edu/~younis/CMSC411/ CMSC411.htm. Lecture’s Overview. Previous Lecture: Constructing an Arithmetic Logic Unit (Different blocks and gluing them together)

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Lecture’s Overview

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  1. CMSC 411-101Computer ArchitectureLecture 8Hardware Design LanguagesFebruary 21, 2001www.csee.umbc.edu/~younis/CMSC411/ CMSC411.htm CMCS 411, Computer Architecture1

  2. Lecture’s Overview • Previous Lecture: • Constructing an Arithmetic Logic Unit (Different blocks and gluing them together) • Scaling bit operations to word sizes • (Ripple carry adder, MIPS ALU) • Optimization for carry handling (Measuring performance, Carry lookahead) • This Lecture: • Design phases • Hardware design languages (HDL) • The “eSim” a simple and miniaturized HDL CMCS 411, Computer Architecture2

  3. Abstraction Hierarchy of Digital Design Digital designers often employ abstraction hierarchy, which can be expressed in two domains: • Structural domain:Components are described in terms of an interconnection of more primitive components • Behavior domain:Components are described by defining the their input/output responses by means of a procedure CMCS 411, Computer Architecture3

  4. Design's Levels of Abstraction CMCS 411, Computer Architecture4

  5. Design Simulator • Device behavioral model is represented by procedure calls • Events that occur within the simulator are kept in a time-based queue • Events are stored as three-tuples (Module #, Pin #, New logic value) • Depending on the behavioral model of a module, the handling of an event usually trigger other events that will be inserted in the event queue Simulation continues until the event queue is empty or stopped externally by the designer CMCS 411, Computer Architecture5

  6. Hardware Design Languages • A hardware design language provides primitive for describing both structural and behavioral models of the design • Hardware design languages are useful in • Documenting and modeling the design • Ensuring design portability • Every hardware design language is supported by a simulator that helps in: • validating the design • mitigating the risk of design faults • avoiding expensive prototyping for complicated hardware • VHDL and Verilog are the most famous and widely used hardware design language • Esim is a simplified and miniaturized version of VHDL to serve undergraduate education CMCS 411, Computer Architecture6

  7. The Esim Design Languages • The esim language is purely digital in which signals can only take values of 0, 1, X for unknown, and Z for high impedance • Esim has primitives for both regular signals and memory, providing an efficient way to simulate microprocessor designs with registers and caches • Esim encourages hierarchical design by allowing the inclusion of modules in other modules • Esim's simulator is implemented as Tcl module, so it can be programmed to provide inputs to particular signals in the circuit • Design files are compiled (ecomp) generating a net list that can be validated through simulation (esim) ecomp test.e -o test.net • As most hardware design lang., all operations run in parallel Esim is developed by Ethan Miller and Jon Squire CMCS 411, Computer Architecture7

  8. Hardware Descriptions in Esim Data types • Signal: • A single signal may have one of four different values: “0”, “1”, “Z” (undriven) or “X” (conflict/indeterminate). • Signals may be aggregated together, e.g. signal inputA[32]; • Memory • Used for register files or main memory • Values in memory remain until explicitly changed by memory statements • Memory can be initialized only using the simulator (not within esim program) Operations CMCS 411, Computer Architecture8

  9. Hardware Descriptions in Esim • Expressions • Expressions may include signals and other expressions combined with operators: out <= (a & b) ^ (d | c) • The number of bits for operands for multi-input operation must match • Binary operators are performed bit-wise producing a result as wide as operands • Equality and inequality operations generate a one-bit results • A value “X” is treated as “do not care” and matches any value in conditional statement • Statements • All statement in esim operate in parallel • A statement takes the format : signal <= expression • Esim Statements can take two types of modifiers: • after: to specify a delay for the execution of the statement • on rising or falling: to specify edge triggered changes Example: a <= b on rising c after 10 ns CMCS 411, Computer Architecture9

  10. Memory Operations • Declaration • Memory simulates variables whose values remain until explicitly changed • The reserved word memory should be used followed by the variable name similar to array declaration in C • Read and write to memory takes the form: <var-name> read <signal> from < expression > [when <expression>] <var-name> write <signal> to < expression > [when <expression>] • Example • memory m[1024]; • signal x[4], y[10], enb, clk; • circuits • m read x from y when enb; • m write x to y[8:2] . #b00 when enb on rising clk; • m write x[3:2] to y when enb; • end circuits; Address in memory CMCS 411, Computer Architecture10

  11. Esim’s Circuit Structure • Components • Basic hardware modules defined in esim are called components • Components may themselves include other components • Every component must be defined before it used. However, there is no limit to nesting levels • Parameters to the component definition do not specify input or output • Internal signals and definitions are not visible outside the component Example: // 8­bit latch clocked on the clk signal when enb1 and enb2 are both enabled • define latch8 (q[8], d[8], enb1, enb2, clk) • signal enabled; • signal qInternal[8]; • circuits • qInternal <= d when (enb1 & enb2) else qInternal; • q <= qInternal on rising clk; • end circuits; • end latch8; • Main Circuit • Use predefined components and do not define new ones • Include design input and output signals and system global memory CMCS 411, Computer Architecture11

  12. Full Implementation of a 32-bit latch • // 8-bit latch clocked on the clk signal when enb1 and enb2 are both enabled • define latch8 (q[8], d[8], enb1, enb2, clk) • ….. • end latch8; • // Set up a 16 bit latch as 2 8-bit latches • define latch16 (q[16], d[16], clk) • circuits • low use latch8 (q[7:0], d[7:0], #b1, #b1, clk); // always enabled • high use latch8 (q[15:8], d[15:8], #b1, #b1, clk); // always enabled • end circuits; • end latch16; • // Top level circuits • signal q[32]; • signal d[32]; • circuits • low use latch16 (q[15:0], d[15:0], clk); • high use latch16 (q[31:16], d[31:16], clk); • end circuits; The names preceding the use keyword allow the user to identify the different instances of latch8 in the simulator * example is courtesy of Ethan Miller CMCS 411, Computer Architecture12

  13. Example • Defining a four way multiplexer with 8 bit signals • // mux4_8 four eight bit inputs controlled by ctl to eight bit out • define mux4_8(A[8], B[8], C[8], D[8], CTL[2], OUT[8]) • circuits • OUT<= with CTL • select • #b00: A; • #b01: B; • #b10: C; • #b11: D; • otherwise: A; // can't happen but need "otherwise" • end select after 1ns; // fast gates • end circuits; • end mux4_8; * example is courtesy of Jon Squire CMCS 411, Computer Architecture13

  14. Example Defining a general register component // “GREG” is general register set // memory is internal: // a1 address reads and outputs on out1 // a2 address reads and outputs on out2 // aw address writes input on wr & clk falling define GREG(a1[5], a2[5], aw[5], input[32], wr, clk, out1[32], out2[32]) memory mr[1024]; // 32 registers of 32 bits each circuits mr read out1 from a1.#b00000 when #b1; // always available mr read out2 from a2.#b00000 when #b1; mr write input to aw.#b00000 when wr on falling clk; end circuits; end GREG; The concatenation is equivalent to word alignment to get the right register * example is courtesy of Jon Squire CMCS 411, Computer Architecture14

  15. Conclusion • Summary • Design phases (Design abstraction, design decomposition) • Hardware design languages (HDL) (Features, benefits, tools) • The “eSim” a simple and miniaturized HDL (Structure, Reserved words, Declaration and statements, examples) • Next Lecture • Algorithms for multiplying unsigned numbers • Booth’s algorithm for signed number multiplication • Multiple hardware design for integer multiplier Reading assignment includes eSim paper and web pages CMCS 411, Computer Architecture15

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