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Steve Miller Chief Engineer

Requirements for Scalable Application Specific Processing in Commercial HPEC. Steve Miller Chief Engineer. The 3 Single-Paradigm Architectures. App-Specific Graphics - GPU Signals - DSP Prog’ble - FPGA Other ASICs. Scalar Intel Itanium SGI MIPS IBM Power Sun SPARC HP PA. Vector

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Steve Miller Chief Engineer

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  1. Requirements for Scalable Application Specific Processing in Commercial HPEC Steve Miller Chief Engineer

  2. The 3 Single-Paradigm Architectures App-Specific Graphics - GPU Signals - DSP Prog’ble - FPGA Other ASICs Scalar Intel Itanium SGI MIPS IBM Power Sun SPARC HP PA Vector Cray X1 NEC SX

  3. Paradigms to Applications Application-specific Application-specific Scalar Vector Low Compute high Intensity Low Data locality High

  4. Architectural Challenges • Hardware • Bandwidth to/from System • Scalability • Software • Compliers/Languages • Debuggers • APIs

  5. Multi-Paradigm Computing UltraViolet Scalar Scalar Vector IO IO Vector Compute FPGA Graphics DSP Reconfigurable Terascale to Petascale Data Set : Bring Function to Data Scalable Shared Memory . Globally addressable . Thousands of ports . Flat & high bandwidth . Flexible & configurable

  6. Software • Provide for HDL modules Integrated environment with debugger Highest performance • Leverage 3rd Party Std Language Tools Celoxia, Impulse Acceleration, Mitrion, Mentor Graphics • Developed an FPGA aware version of GDB Capable of debugging the FPGA and System Software Capable of multiple CPUs and multiple FPGAs • Developed RASC Abstraction Layer (RASCAL)

  7. Software Overview Download Utilities Debugger (GDB) Application User Space Abstraction Layer Library Device Manager Algorithm Device Driver Download Driver Linux Kernel COP (TIO, Algorithm FPGA, Memory, Download FPGA) Hardware

  8. Abstraction Layer: Algorithm API Algorithm Application Input Data COP Input Data Algorithm Output Data Output Data COP COP COP COP Application • The Abstraction Layer’s algorithm API mirrors the COP API with a few additions that enable wide scaling, • and deep scaling.

  9. Hardware • Direct Connection to NUMAlink4 • 6.4GB/s/connection • Fast System Level Reprogramming of FPGA • Atomic Memory Operations Same set as System CPUs • Hardware Barriers • Configurations to 8191 NUMA/FPGA connections

  10. MOATB Block Diagram 2MB QDR SRAM Addr & Ctrl 36 36 Addr & Ctrl Addr & Ctrl Algorithm FPGA 36 36 2MB QDR SRAM 2MB QDR SRAM 36 36 Select Map Programming Interface Loader FPGA SSP 72 72 TIO PCI 66MHz NUMAlink Connectors NUMAlink 12.8 GB/s SSP 6.4 GB/s QDR SRAM 9.6GB/s 3 reads @ 1.6GB/s 3 writes @ 1.6GB/s

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