1 / 32

FTK Status – future developments

b. FTK. e. m. b. t. b. m. b. b. t. h. e. t. FTK Status – future developments. OUTLINE sblocco SJ – Conditons : TDR – MOU - chip design PERFORMANCES in the TDR Italian role in FTK. Paola Giannetti for the FTK collaboration.

clinton-dawson
Download Presentation

FTK Status – future developments

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. b FTK e m b t b m b b t h e t FTK Status – future developments OUTLINE sblocco SJ – Conditons: TDR – MOU - chip design PERFORMANCES in the TDR Italian role in FTK Paola Giannetti for the FTK collaboration Gruppo 1, incontro con I referees, Luglio 8 – 2013

  2. Sblocco SJ: 222 keuroperordine di AMchip06 Conditions to be satisfied: (1) solid Italiancollaboration, (2) adeguate coverage of costs, (3) design of Amchip done. • Italian Group is growing fast (FTE: 11,90 in 2012, 18,1 in 2014) • FTK TDR with simplified, but very interesting physics case - printed version: https://cds.cern.ch/record/1552953?ln=en In the TDR: Solid collaboration has been defined with sharing of responsibilities and costs • For Amchip design see later in the talk

  3. The team & cost sharing Possible extra costs Possible extra Joined recently, after the 2010 review

  4. AMCHIP status • MiniAsicjust received - ongoing tests at Milan • Design of AMchip05 • (LPNHE-MI-LNF-PI-) advanced – Submission during summer if IP core (SerDes) is working correctly • Design of AMchip06 expected for spring 2014

  5. DOI:10.1109/ANIMMA.2011.6172856 AMchip04(1) AM chip04: TMSC 65 nm with Variable Resolution MI-LNF-PI-LPNHE Even IF power consumption is as expected Core Power Consumption has to be decreased because of increase due to Serialized I/O custom cell to reduce pattern size & consumption 8k patterns in 14 mm^2.

  6. IF final Chip power < 2W & AUX power < 75 W ~ 1.2 kW on the back This is ~ the limit for (a) Standard PS availability (b) cooling

  7. COOLING TESTS IN PAVIA (A. Lanza) 4.5 kW in front crate ~ 4500 W

  8. TESTS reported here WITH CDF FANs • We are confident we can cool ~ 5 kW • Next Steps: • Turn on the chillerto cool the air • Use last-version of Wiener fans to see if improved power gives better results • Close the Wiener fans on the sides. • Turn on two old AMBoards (or 3) and see if they work correctly • Last: try the final boards and final chips in the crate

  9. AMchip05 design

  10. Changes in LOGIC (LPNHE): • SERDES I/O @ 16 bits (2 DC)(AMchip04 was 15 bits 3 DC. Internally it's always 18 bits with configurable DC) • Two pattern inputs one pattern output (merge of pattern streams) • 1-layer match threshold (other thresholds: never, 8, 7, 6, always) • double width mode (4 bus - 32 bit) • optional continuous readout mode(AMchip04 was event based only) • Change for implementation of design • Majority inside pattern becomes full custom (MILAN) • New Low Power full custom cell for pattern (LNF) New features wrt AMchip04 Milan

  11. LNF The Low Voltage /very Low Power Cell expectations: promising But very large uncertainty AMchip Review July 8 - 2013

  12. Conclusion for the SJ • AMchip06 design is not ready (expected to be ready spring 2014) but it is like AMchip05, only larger, and: • Complex order ~500 keuros, involves 6 funding agencies! To be prepared in advance, money must be ready months before the submission. • AMchip05 in advanced status, all the relevant features are there • Miniasictests will allow to check the status of IP cores before AMchip05 submission • We will care about not submitting AMchip06 if the IP core will not work in the miniasic. • If the order of AMchip05 is delayed by Monday review to end of September, we can wait September for the SJ release.

  13. Tau Physics case: one example from the TDR ET>15 GeV Fcore>0,75 Standard Level-2: calorimeter’s cuts to lower the rate before performing tracking

  14. RSIG RI RISO Jet axis FTK Selection with no calorimeter action before leading PT trackin ROi (Ri in figure) Rsig= 0,1 & Riso=0,3around leading track; 1 (1-prong) or 2-3 (3-prong) tracks in Rsig; Count tracks in Riso.

  15. Results Tau EFFICIENCY Tau Pt spectrum from light H Rejection of fake tau

  16. Other arguments in the FTK TDR 3.2.1 Lepton Isolation 3.2.2 b-jet tagging 3.2.3 Primary Vertex Finding To be added to TDAQ TDR in September association Jet-primary vertex (fraction track energy coming from prim. Vertex Track correction to MET

  17. Project organization-Italian responsibilities

  18. The team and task sharingThe Italian role today

  19. In addition to Amchip design.. Rewriting FTK_IM clustering firmware - testing new protototypes Designing boards for Miniasic, AMchip05, AMchip06. AMBSLP miniLamb X miniasic LambSLP X AMchip05, 06 PISA - CERN – PRIELE inside IAPP

  20. Design Frascati + Waseda First tests @ Waseda • FTK_IM prototype compatible with DF via FMC connector. • Problem with power generator solved (changed component) • Output to DF tested up to 400 MHz (design) for some lines. • New requirement from DF: more lines at 400MHz being tested.

  21. A new “VariableResolution Associative Memory” for High Energy Physics ATL-UPGRADE-PROC-2011-004 doi:10.1109/ANIMMA.2011.6172856 low S/N AMchip04 High S/N HW limits satisfied with variable resolution 1 layer

  22. Not USA responsabilitiescost sharing – 2014 -2017 ITALIA core 2013: = 220keuro AMchip06 ITALIA core 2014: 135 (FTK_IM)+ 30 (AMBSLP) + 120 (tests parzialmente SJ) = 285keuro ITALIA core 2015: 80 (AMBSLP)+200 wafers = 280keuro ITALIS core 2016-2017: = 390keuro AMBSLP + qualchespesapiccola non-core

  23. Conclusions • Complex orders for Amchip object of SJ release • There is good progress on all of the hardware components. • Nice results for the physics case. • FTK collaboration is growing in particular Italy • Italian group has an important role (see backup) • Share of costs is defined – extra costs already appears, but new funding agencies can provide more than what in TDR table • Italian Core costs ~flat, still in evolution

  24. BACKUP

  25. ITALIAN Responsibilities • Project Manager - M. Shochet (Chicago) • Deputy Project Manager - P. Giannetti (Pisa) • Task • FTK_IM - M. Beretta (Frascati) • AMBoard - M. Piendibene (Pisa) • LAMB – P. Giannetti (Pisa) • AMBoard and LAMB firmware - D. Magalotti (Perugia) • AM chip - A. Stabile (Milan), F. Crescioli (Paris) • System Integration • Tests & board integration in the Vertical Slice - M. Piendibene(Pisa) • DAQ integration: Vertical Slice/Demonstrator - A. Annovi (LNF) • Rack integration: p. supplies, cooling, & safety - A. Lanza (Pavia) • Interface to level-2 - J. Zhang (Argonne), A. Negri (Pavia), A. Annovi (LNF) • FTK simulation - G. Volpi (LNF)

  26. TALKS to Italians 2012-13 2 PRINs + 1 FIRB @ second selection + 2 FP7 People projects ongoing

  27. STd Power Supply - Tot~5320 W • 5V: AUX expected need ~75 W→15 A/AUX →15 A*16 = 240 A+ some spare current for VME → requested 260-270 A- ~ 1350 W; Wiener proposal: 3 modules 115 Aeach for a total of 345A • 14 V: AMchip core; goal~128 W→9.2 A/AMB→9.2 A *16 = 147 A-2048W Wiener proposal: 4 modules @15 V 550 Weach for a total of 2200 W • @14 V184 A 2200 W • 48 V: for SerDes and fanouts: ~120 W→2,5 A/AMB →2,5 A *16 = 40 A • 1920 W • Wiener proposal: 3 modules 13.5 Aeach for a total of40.5 A

  28. CAEN How to fit 3 crates - Too long cables? PS in the middle? RACK OPTIONS Green ~cable length assuming Bins have Connection tools on top & PS output on top & bottom CAEN IDEA 1 single PS For 2 crates In the middle

  29. UNCERTAINTIES on made IPOTHESIS • Will AMCHIP core consumption be < 2 W /128 kpatterns ?? • Will AUX / SSBboard consumption be ~ 75 W ?? • Which fan we will choose? 2 Unit fan or 1 Unit fan ?? • Which power supplies we will use? • Wiener 6 Units PS, one per crate • CAEN 9-10 Units PS, one for 2 crates. • On 3 and 4 + eventual need of extra crates will influence the cost • Proposal: lets use what we have for 2015 as much as possible, let’s buy new stuff when uncertainties above are clarified. • RACK will be defined at that moment.

  30. (8) The AM system schedule Installation of the first 8 PUs expected at the beginning of 2015

  31. o 40-60 Unit fan: air mixed before crate But 1 unit distance between wheel and crate

More Related