1 / 19

Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott Mahlke Advanced Computer Architecture Lab.

Parallelizing Sequential Applications on Commodity Hardware Using a Low-Cost Software Transactional Memory. Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott Mahlke Advanced Computer Architecture Lab. University of Michigan. Multicore Architectures. Industry wide move to multicore

clive
Download Presentation

Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott Mahlke Advanced Computer Architecture Lab.

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Parallelizing Sequential Applications on Commodity Hardware Using a Low-Cost Software Transactional Memory Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott Mahlke Advanced Computer Architecture Lab. University of Michigan 1

  2. Multicore Architectures • Industry wide move to multicore • Higher throughput • More power efficient • Great for parallel programs • Sequential see little benefit Intel 4 Core Nehalem AMD 4 Core Shanghai Sun Niagara 2 IBM Cell 2

  3. Loop Parallelization Parallelizable loop i = 20-39 i = 0-19 i = 0-39 Bad news: limited number of parallel loops in general purpose applications No cross-iteration register or memory dependences Core 1 Core 0 [Zhong ‘08] 3

  4. Loop Parallelization SPECfp [Zhong ‘08] 4

  5. Speculative Loop Parallelization Speculatively parallelizable loop Loop Chunk i = 10-19 Pointer? i = 0-9 Pointer? i = 0-39 Pointer? i = 30-39 Pointer? i = 20-29 Pointer? Memory address is unresolvable statically Core 1 Core 0 5

  6. Speculative Loop Parallelization 6

  7. Supporting Thread Level Speculation • Execution of speculative loops requires • Conflict detection • Rollback mechanism • Speculation can be supported by transactional memory • Software is slow • Hardware needs complex structures • Previous TLS works require hardware • Hydra [Hammond ‘98], Stampede [Steffan ‘98], POSH [Liu ‘06] 7

  8. Objectives • Challenge • Can we get speedup supporting speculative loop parallelization without additional hardware? • Build a specialized software system • Provide functionality needed for speculation with software transactional memory • Leverage existing loop parallelization framework from [Zhong ‘08] • Tightly couple STM with compiler to ensure low overhead 8

  9. Traditional STM Execution Flow Execution Transaction Execute TX TX Commit WritebackWrSet to Memory Start TX End TX RdSet WrSet Consistency Check Abort Commit High Overhead: Validating RdSet High Overhead: Global Locking 9

  10. Ordering Transaction Commit • TMs typically have no way of controlling commit order • Loop iterations must commit in original order • Ensures proper rollback • Requires centralized control to enforce ordering TX 1 TX 2 i = 10-19 i = 0-9 TX 3 TX 4 i = 30-39 i = 20-29 Core 0 Core 1 10

  11. STMlite • Dedicated thread to control commits • Called the Transaction Commit Manager (TCM) • Performs consistency checks for all transactions • Provides point to easily enforce in-order commit • Bloom-filter based signatures • Hash read and write sets • Similar technique used by HTMs like Bulk [Ceze ‘06] • Low-cost consistency checks during commit 11

  12. Bloom-Filter Based Signatures • Constant time insertion and find • Linear time intersection (bitwise OR) Address 101 100 101 010 Decode Signature (Bit array) 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 12

  13. STMlite Execution Flow Execution Transaction Execute TX TX Commit WritebackWrSet to Memory Start TX End TX RdSig WrSig Flag Ready RdSet WrSet Consistency Check Abort Ready Commit Abort Commit Transaction Commit Manager (TCM) Wait for Ready Consistency Check 13

  14. Experimental Setup • Implemented framework in LLVM Compiler • Benchmarks • Stanford STAMP transactional benchmarks • SPECfp benchmarks • Run on Sunfire T2000 • 8-core UltraSPARC T1 processor • Baseline STM is Sun’s TL2 [Dice ‘06] 14

  15. STAMP Benchmarks 15

  16. SPECfp Benchmarks 16

  17. Conclusion • STMlite • Customized for speculative loop parallelization • Transaction commit ordering • Centralized consistency checks • Hashing read/write sets with signatures • Parallelization of sequential applications is feasible on commodity hardware • Removes much of the slowdown traditionally associated with STM 17

  18. Thank You! Questions? 18

  19. Transaction Execution and Commit • Stale entries periodically removed from commit log Executing Checking Waiting Waiting Writeback Waiting Transaction Transaction Commit Manager (TCM) Commit Ready Start End End Commit Log Consistent? RdSig WrSig WrSig Consistent? End WrSig Consistent? End WrSig End WrSig 19

More Related