Technische Universität München

1. Technische Universität München Beyond GORDIAN and KRAFTWERK: EDA Research at TUM We create tools for chipsInstitute forElectronic Design AutomationU. SchlichtmannISPD 2015 - March 31, 2015

2. Overview The early years Plantage: Analog Placement PROTON: ONoC Physical Design

3. Topics covered by Prof. Antreich • Since 1975: CAD for analog circuits • Early 1980s: Physical Design • Mid-1980s: ATPG • Late-1980s: Digital Simulation (Parallelization) • 1990s: Logic and RTL synthesis (FPGAs) • 1990s: Formal Techniques

4. Topics covered by Prof. Antreich • Since 1975: CAD for analog circuits • Early 1980s: Physical Design • Mid-1980s: ATPG • Late-1980s: Digital Simulation (Parallelization) • 1990s: Logic and RTL synthesis (FPGAs) • 1990s: Formal Techniques

5. Can you simulate what you want to design? Mathematical View Performances f Circuit simulation Physical View Parameters x Abstraction from the physical level Simulation:

6. Normal distribution of with mean vector covariance matrix Statistical Parameter Distribution

7. Operating range Bounds for environmental parameters Simulator input Performance specification Bounds for performances Simulator output Operating Range, Performance Specification

8. Realistic Worst-Case Analysis • Linear performance model with gradient for each performance • Parameter tolerance ellipsoid

9. Relate Yield and Tolerance Region: Worst-Case Distance W sigma design

10. Example – Yield (Worst-Case) Analysis Nominal value Specifi- cation Worst-case distance/yield Performance 76 Gain[dB] ≥ 65 2.5(„“)/99.4% 67 Transit frequency [MHz] ≥ 30 7.7(„“)/99.9% 68 Phase margin[º] ≥ 60 1.8(„“)/96.9% 67 Slew rate [V/s] ≥ 32 6.3(„“)/99.9% 2.6 DC power [mW] ≤ 3.5 1.1(„“)/86.4% 82.9% Overall yield

11. Example – Yield (Worst-Case) Analysis Worst-case distance Yield partition 99.99% 97.70% 50.00%

12. Example – Optimized Yield Yield partition Worst-case distance 99.99% 97.70% 50.00%

13. Vision & Mission: Empowering Innovation EDA Software Vendor – Design Tool Suite WiCkeDTMfor IP Migration, Analysis, Modeling & Sizing of Nanometer IC designs Founded in 2001 - Headquarters in Munich Germany Worldwide Sales & Support Offices in USA, Korea, China, Taiwan, Japan, UK, Ireland, Scandinavia, South America Worldwide Customer Base of Semiconductor IDMs, Fabless Design Houses & Foundries MunEDA Corporate Overview

14. MunEDA Worldwide Customers & Foundry Partners (Selection) and more… for WiCkeDTM customer references see http://www.muneda.com/Customers

15. Overview The Early Years Plantage: Analog Placement PROTON: ONoC Physical Design

16. manual mostly automated mostly manual Analog Design Flow Specification Topology Sizing Sizing rules Placement Placement rules Routing rules Routing Layout Process variations Parasitics etc.

17. R1 R2 R3 R4 R5 R6 close proximity variant constraints Placement rules E A A1 B2 A3 B4 C A B C B C D B1 A2 B3 A4 A B E common centroid E symmetry alignment minimum distance Modeling: linear (in-)equalities Modeling: inter-set relations

18. State-of-the-Art • Two classes of algorithms: • Absolute coordinates • [Jepsen/Gellat, ICCD‘83] • [Kohn/Garrod/Rutenbar, IEEE Journal SC‘91] • Topological relations • Sequence Pair [Murata/Fujiyoshi, TCAD‘96], [Tam/Young/Chu, ICCAD‘06] • BSG [Nakatake/Fujiyoshi, ICCAD‘96] • B*-Tree [Chang/Chang, DAC‘00], [Balasa, TCAD‘04], [Lin/Lin, DAC‘07], [Lin, DAC‘08] • Optimization using Simulated Annealing

19. OPA CM CORE M8 C DS DP DS CM DP CM CM M5 M6 M7 M1 M2 M3 M4 Hierarchically Bounded Enumeration • Hierarchical structure of analog circuits • Automatic structure recognition [Gräb, Zizala, Eckmüller, Antreich ICCAD‘01] [Massier, Gräb, Schlichtmann DATE‘08] M5 M6 M7 C M1 M2 M8 M3 M4 CM: Current Mirror DP: Differential Pair DS: Differential Stage

20. … M8 C M8 M8 C C OPA M8 C CORE M8 C Fundamental module sets M5 M6 M7 DS M1a M2a M3 M4 CM DP CM M5 CM DP CM M2b M1b M5 M6 M7 M7 M6 M1 M2 M4 M3 M4 M4 M3 M5 M6 M7 M1 M2 M3 M4 … … M3 … M5 M7 M6 M1a M2a M1b M2b Hierarchically Bounded Enumeration OPA Enumeration of placements of fundamental module sets CORE DS

21. … M8 C M8 M8 C C M5 M6 M7 CM M8 C DS M5 M6 M7 C DP M1 M2 M1a M2a M3 M4 CM DP CM M5 M8 M3 M4 CM M2b M1b M5 M6 M7 M7 M6 M1 M2 M4 M3 M4 M4 M3 … … M3 … M5 M7 M6 M1a M2a M1b M2b Overview • Hierarchical approach • Enhanced shape functions • New algorithm for placement:B*-Tree  CG  LP • New addition of shapesby addition of B*-Trees OPA CORE DS Enhanced Shape Functions Enhanced Shape Addition

22. Results • OTA with folded cascode DP WSCM DP #8 WSCM #3 optimum area 12 shapes in 44 s WSCM: Wide Swing Cascode current Mirror DP: Differential Pair #10

23. Industrial Example: wls_input_stage (c) (b) (a) (a) (b) (c)

24. Overview The Early Years Plantage: Analog Placement PROTON: ONoC Physical Design

25. The Architecture Array of off-chip CW lasers λ2 λ3 λ4 λ1 Off-chip memory H1 H3 1 T SV 3 M1 T SV M3 2 4 M2 M4 H2 H4 T SV T SV Photonic layer Electronic layer Clusters of processors

26. The Photonic Layer λj H1 H3 M3 λi M4 M2 H4 H2 • A path connects two Hubs or a Hub and a Memory Controller via Photonic Switching Elements (PSEs) and waveguides λi λj M2 H3 Memory Controller PSE Hub PSE M1 Photonic layer

27. Example: LogicSchemeofOptical Layer λ4 I2 λ1 I1 O1 O2 Wavelength λ1isredirected Wavelength λn crosses Example: 8x8 λ-Router [Scandurra NoCArc’08]

28. Logic Scheme vs. Physical Design M1 M3 H3 H1 H4 H2 M4 M2 Manually created layout [Ramini NOCS’12] Logic Scheme Creating layout manually is time consuming,error prone and suboptimal PROTON:The first automatic place & route tool for 3D optical NoCs

29. Placement and Routing Problem Netlist, chip area, positions of hubs and memory controllers • Minimize maximum insertion loss over all paths, e.g. minimize • Waveguide length • Number of crossings between waveguides • Number of bends • Constraints: • Place all PSEs and waveguides inside chip area • No overlap Valid and optimal layout

30. Placement and Routing Algorithm Placement Routing • Approximate waveguide length of each path by using a quadratic net model • Approximate number of crossings • Solve non-linear optimization problem • Route waveguides by allowing but penalizing crossings • E.g. Maze Router

31. Approximation of Crossings • Approximated number of crossings is calculated with the weights of Simpson’s rule Module s Module i Module j Module r

32. Solving the Optimization Problem • Find positions of all PSEs • Constraints • Place all PSEs inside chip area • No overlap between optical devices (PSEs, hubs, memory controllers) • Nonlinear Optimization Problem solver: IPOPT (Interior point method)

33. Manual Layout vs. PROTON

34. Contributions & Acknowledgements • Anja von Beuningen • Helmut Graeb • Martin Strasser • Michael Eick • Frank Johannes

35. TUM. Technische Universität München