Shift Instructions (1/4)

1. Shift Instructions (1/4) • Move (shift) all the bits in a word to the left or right by a number of bits. • Example: shift right by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000 0000 00000001 0010 0011 0100 0101 0110 • Example: shift left by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000 0011 0100 0101 0110 0111 10000000 0000

2. Shift Instructions (2/4) • MIPS Shift Instruction Syntax: 1 2,3,4 • where 1) operation name 2) register that will receive value 3) first operand (register) 4) shift amount (constant < 32, 5 bits) • MIPS shift instructions: 1. sll (shift left logical): shifts left and fills emptied bits with 0s 2. srl (shift right logical): shifts right and fills emptied bits with 0s 3. sra (shift right arithmetic): shifts right and fills emptied bits by sign extending

3. Shift Instructions (3/4) • Example: shift right arith by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000 0000 00000001 0010 0011 0100 0101 0110 • Example: shift right arith by 8 bits 1001 0010 0011 0100 0101 0110 0111 1000 1111 11111001 0010 0011 0100 0101 0110

4. Shift Instructions (4/4) • Since shifting may be faster than multiplication, a good compiler usually notices when C code multiplies by a power of 2 and compiles it to a shift instruction: a *= 8; (in C) would compile to: sll $s0,$s0,3 (in MIPS) • Likewise, shift right to divide by powers of 2 • remember to use sra

5. Signed extend partial product at each stage Final step is a subtract n-clock cycles “Shift and Add” Signed Multiplier

6. Fast multiplication hardware

7. Chap.5 The processor: Datapath and control Jen-Chang Liu, Spring 2006

8. Application (Netscape) Operating Compiler System (Windows 98) Software Assembler Instruction Set Architecture Hardware Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors Hierarchy of Machine Structures

9. Five components of computer • Input, output, memory, datapath, control

10. Inside Mother board (for Pentium Pro)

11. Chapter overview • Chap5: datapath and control • Chap6: pipeline • Chap7: memory hierarchy • Chap8: I/O • Chap9: multiprocessor Inside CPU

12. Inside Processor: datapath and control • Datapath: brawn of the processor • Perform the arithmetic operations • Control: brain of the processor • Tells the datapath, memory, and I/O what to do 生產線

13. Inside Pentium Processor 1/3 cache

14. Inside Pentium Pro Processor

15. Clocks methodology high low Edge-triggered clocking: the content of the state elements (flip-flops, registers, memory) only change on the active clock edge 101 001 111 100 001 110 100

16. Timing constraint • The clock period must be long enough to allow signals to be stable

17. Design Target: MIPS • The instruction set architecture (ISA) determines the implementation • We know how to execute MIPS codes manually, how to design a circuit to execute them? • We design a simple implementation that includes a subset of MIPS inst. • Memory-reference inst.: lw, sw • Arithmetic-logic inst.: add,sub,and,or,slt • Branch: beq, j

18. Outline of chapter 5 • Building a datapath • Instruction fetch • R-type instructions • Load/store • Branch • Single Datapath implementation • Multiple cycle implementation

19. Preview: How to carry out an instruction • 4 steps to implement an instruction 執行 Instruction fetch Data/register read Instruction execution Memory/register read/write Read inst. from memory ALU add $t0, $t1, $t2 Write to $t0 $t1, $t2 $t1 + $t2 $a0 Read from memory lw $t0, 0($a0) $a0 + 0 $t0 - $t1 beq $t0, $t1, loop $t0, $t1 Write PC

20. Abstract view of carrying out an instruction Instruction fetch Data/register read Instruction execution Memory/register read/write

21. How to build datapath for MIPS ISA? • Datapath: path to perform an instruction • Consider each major components • Build datapath for each instruction class

22. Outline • Building a datapath 1. Instruction fetch 2. R-type instructions 3. Load/store 4. Branch Build datapath for each instruction class, then combine them

23. 1. Instruction fetch Increment the PC to next instruction Address of the instructions Place to store the instructions

24. Instruction fetch (cont.) 3 always adds, therefore no control lines 1 2

25. Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 2. R-type instruction • R-format instructions • Arithmetic-logic instrcutions • add, sub • Ex. add $t1, $t2, $t3 • and, or • slt

26. Datapath elements for R-type inst. 4 input output 1. Read register: read register no., output data 2. Write register: write register no., input data, RegWrite=1

27. Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 Datapath for R-type inst. 4 2 1 3

28. Opcode 6 rs 5 rt 5 Signed offset 16 3. Load/store from/to memory • I-format • Load/store examples • lw $t1, offset_value($t2) • sw $t1, offset_value($t2) … offset $t2

29. lw $t1, offset_value($t2) Datapath elements for load/store • Register file, ALU, and data memory Base+offset Sign-extend the 16-bit offset field Store -> MemWrite Load -> MemRead

30. Opcode 6 rs 5 rt 5 Signed offset 16 Datapath for load/store 4 2 1

31. Opcode 6 rs 5 rt 5 Signed offset 16 4. Branch • I-format • Example • beq $t1, $t2, offset • PC-relative addressing

32. Opcode 6 rs 5 rt 5 Immediate 16 Details for branch: target address calculation • Base address for offset: PC+4 • Instructions are word-aligned: the offset is shifted left 2 bits … PC+4 offset 00 offset

33. Opcode 6 rs 5 rt 5 Signed offset 16 Datapath for branch 2 4 1

34. How to combine these datapaths ? • We have shown datapaths for • Instruction fetch • R-type instructions • Load/store • branch • How to assemble the datapaths? • How to handle control lines?

35. Outline • Building a datapath • Instruction fetch • R-type instructions • Load/store • Branch • Single Datapath implementation • Multiple cycle implementation

36. Single datapath implementation • Attempt to execute all instructions in 1 clock cycle • No datapath resources can be used more than once per instruction • Duplicated units: ex. Memory for instructions and memory for data • Shared units: use multiplexor to select input add,… 生產線 lw, sw beq,…

37. Opcode 6 rs 5 rt 5 rd 5 shamt 5 funct 6 Opcode 6 rs 5 rt 5 Signed offset 16 1. Combine R-type and lw/sw 4 R-type 4 lw/sw

38. R-type + load/store 4 2 1

39. 2. Add the instruction fetch 4

40. 3. Add the branch unit 4

41. Simple datapath and control. See Fig 5.17 (p.307)

42. Trace the operation of the datapath !!! • Explain in 4 steps, but they are actually operates in a single clock cycle • Quiz later !!! Instruction fetch Data/register read Instruction execution Memory/register read/write

43. add $t1,$t2,$t3 => add $9, $10, $11 => Step 1. Instruction fetch

44. add $t1,$t2,$t3 => Step 2. Read source registers

45. add $t1,$t2,$t3 => Step 3. Instruction execution

46. add $t1,$t2,$t3 => Step 4. Write result

47. lw $t1, 0($t2) 9 10 0 36

48. How to combine the datapaths ? • We have shown datapaths for • Instruction fetch • R-type instructions • Load/store • branch • How to assemble the datapaths? • How to handle control lines?

49. Simple datapath and control. See Fig 5.19 (p.360)

50. How to generate control? 6 bits 6 bits Truth table look-up 10 bits Control signal