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4. Combinational Logic Networks . 4.2 Layout Design Methods 4.2.1 Single Row Layout Design

4. Combinational Logic Networks . 4.2 Layout Design Methods 4.2.1 Single Row Layout Design. Power rails Routing chnnel n-type, p-type row. Intra-row Routing area. Structure of a routing channel. Horizontal tracks and vertical tracks Channel Density, changed with pin assignment.(below).

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4. Combinational Logic Networks . 4.2 Layout Design Methods 4.2.1 Single Row Layout Design

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  1. 4. Combinational Logic Networks.4.2 Layout Design Methods4.2.1 Single Row Layout Design • Power rails • Routing chnnel • n-type, p-type row Intra-row Routing area

  2. Structure of a routing channel • Horizontal tracks and vertical tracks • Channel Density, changed with pin assignment.(below)

  3. Layout of a full adder • Swap the gates within each function • Swap the XOR pair with NAND networks

  4. Left-edge channel routing • Optimum under assumption that only one horizontal wire segment per net. Channel that cannot be routed by the left edge algorithm (Vertical constraint) A dogleg wire

  5. 4.2.2 Standard Cell Layout Design • Cell from library NAND, NOR, AOI, OAI • The same pitch (height) • VDD and VSS lines must match up. • External connection points are on the top and bottom edges. • Cell area cannot be used for wiring. • Feedthrough area for short cut of critical pathes. • Transistor sizes are typically much larger than those in custom layouts.

  6. Wireability of placement • Rat’s nest plot to identify congested area, whose degree of congestion will be minimized.

  7. 4.3 Simulation • Circuit Simulation • Timing Simulation • Switch Simulation • Gate Simulation (Logic Simulation) Propagate new value until it will be stable

  8. 4.4 Combinational Network Delay4.4.1 Fanout • Transistors of driving gate can be enlarged. • Logic can be redesigned to reduce the gate’s fanout.

  9. 4.4.2 Path Delay • Timing Analysis identifies critical path with graph model, instead of exhausted search with logic simulator.

  10. Critical Path Cutset of critical path: increase transistor size reduce wire capacitance

  11. False Path • True Path determines timing constraint.

  12. a(b+c(d+ef)) ab+acd+acef Redesign for speed up

  13. 4.4.3 Transistor Sizing • 0.5nsec delay/stage All p: 1.5/0.5 1 0 1 1 0 All n: 0.75/0.5

  14. Transistor Sizing (Continue) Pull up: 1.5/0.5  4.5/0.5 (first stage) 3.0/0.5(other stages) • 0.25nsec delay/stage 2 times as faster as before 1 0 1 1 0 Pull down: 0.75/0.5  1.5/0.5 0.75/0.5  1.5/0.5

  15. Transistor Sizing (Continue) Pull up: 1.5/0.5  4.5/0.5 (first stage) 3.0/0.5(other stages) • 0.125nsec delay/stage 4 times as faster as before 1 0 1 1 0 Pull down: 0.75/0.5  1.5/0.5 0.75/0.5  3/0.5

  16. 4.5 Crosstalk • Crosstalk depend on • Adjacent area • Behavior of 2 signals

  17. Crosstalk (continue) • Ground wires to minimize crosstalk

  18. Crosstalk (continue) • Crosstalk minimization by wire routing Total coupling=17 Total coupling=12 (a-b=6, b-c=6, c-d=5) (a-b=5, a-d=2, d-c=5)

  19. 4.6 Power Optimizationby reducing glitches Glitch  power • Glitches propagate through the successive stage.  the longer chain produces much glitch.

  20. Power Optimization (continue) • Signal probability Ps: the probability that signal s is 1. • Probability of a transition Ptr,s: the probablity that signal changes from 0 to 1 or from 1 to 0. Ptr,s=(1-Ps)Ps+Ps(1-Ps)=2Ps(1-Ps) • Power estimation tools based on delay independent assumption PNOT=1-Pin POR=1-(1-Pin1)(1-Pin2) PAND=Pin1 Pin2

  21. Logic factorization for low power

  22. 4.7 Switch Logic Networks • Switch Logic is not universally useful. • Slow • introduce hard-to-trace electrical • problems • lack of drive current for high • capacitive load Switch network with non-constant source inputs. Swicth implementation of a multiplexer

  23. Switch Logic Networks (continue) 10 10 10 • Voltages are dependent on capacitance ratios, which cannot be controlled. • Table shows possible voltage change of nodes. 10 Output remains 11 (Output should be undefined)

  24. Switch Logic Networks (continue)Charge Sharing • Voltages are dependent on capacitance ratios, which cannot be controlled. • Table shows possible voltage change of nodes.

  25. 4.8.1 Gate Testing • fault model (stuck-at-0/1) NAND NOR

  26. Gate Testing (Continue) 0 1 Vector(011) for 2 NANDs stuck-at-0 test 1 1 1 - 1 Vector(11-)(-01) for 2 NANDs stuck-at-1 test 0 1 1 -

  27. Stuck-Open fault • t1 stuck-open fault makes gate not to pull up to VDD. • t2 stuck-open fault makes gate pull down to VSS, conditionally. • Delay fault • Gate delay fault • Path delay fault

  28. 4.8.2 Combinational Network Testing Job1: either 1 must be set. • Controlling the gate’s inputs by applying values to the network’s primary inputs. • Observing the gate’s output by inferring its value from the values at the network’s primary outputs. Stuck-at-0 Job2: Dout 0 or 1 to be observed at primary output.

  29. Fault Masking • NOR output sa0 (“1”) cannot be set. • NAND output sa0 (“1”) cannot be observed at primary output. • F=[(ab)’+b] =[a+b’+b] =0 Logic is untestable, Because of rudundant.

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