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Traditional IBM Mainframe Operating Principles

17. Traditional IBM Mainframe Operating Principles. Fig. 17.1: The memory hierarchy. Addressing Memory. Absolute addresses counting bytes hardware Relative addresses base plus displacement software At load time, base address stored in base register.

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Traditional IBM Mainframe Operating Principles

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  1. 17 Traditional IBM Mainframe Operating Principles

  2. Fig. 17.1: The memory hierarchy.

  3. Addressing Memory • Absolute addresses • counting bytes • hardware • Relative addresses • base plus displacement • software • At load time, base address stored in base register

  4. Fig. 17.2a: The program status word, BC mode.

  5. Fig. 17.2b: The program status word, EC mode.

  6. Fig. 17.2c: The program status word, XA mode.

  7. Fig. 17.3: A program segment.

  8. Executing Instructions • Find instruction address in PSW • Fetch instruction stored at that address • Increment instruction address • Translate instruction’s operands • Execute instruction

  9. Fig. 17.4: Instruction formats.

  10. Other PSW Fields • Condition code • key to decision logic • set by comparison and arithmetic instructions • Memory protection • 4-bit protection key • associated with each block of memory • access to wrong key causes interrupt

  11. Fig. 17.5: The channel command word (CCW).

  12. Fig. 17.6: The channel address word (CAW).

  13. Fig. 17.7: The channel’s processor looks to the CAW to find the first CCW.

  14. Fig. 17.8: The channel status word (CSW).

  15. Fig. 17.9a: The program calls the access method. Note: Certain instructions are privileged, so a program must call the operating system to start I/O.

  16. Fig. 17.9b: The operating system stores the address of the channel program in the CAW and starts I/O.

  17. Fig. 17.9c: The channel fetches the first CCW.

  18. Fig. 17.9d: The channel signals the main processor.

  19. Fig. 17.9e: The operating system returns control to the application program.

  20. Fig. 17.10: Interrupt response.

  21. Fig. 17.11a: The current PSW points to the application program.

  22. Fig. 17.11b: When an interrupt occurs, the current PSW is stored in the old PSW field.

  23. Fig. 17.11c: The new PSW is loaded into the current PSW register.

  24. Fig. 17.11d: The first instruction in the interrupt handler routine is fetched.

  25. Fig. 17.11e: The old PSW is loaded into the current PSW and the application program resumes processing.

  26. Interrupt Types • External • Supervisor call • Program • Machine check • I/O • Restart

  27. Fig. 17.12: An external interrupt.

  28. Fig. 17.13: An SVC interrupt.

  29. Fig. 17.14: A program interrupt.

  30. Fig. 17.15: A machine check interrupt.

  31. Fig. 17.16: An I/O interrupt.

  32. Fig. 17.17: Fixed locations in memory.

  33. Fig. 17.18a: Following an interrupt, the link back to the program is stored in the old PSW. Two or more interrupts occurring in a brief time span can destroy the trail back to the original program.

  34. Fig. 17.18b: The second interrupt overlays the link, thus destroying it.

  35. Fig. 17.19a: Masking interrupts, BC mode.

  36. Fig. 17.19b: Masking interrupts, EC mode.

  37. Fig. 17.20: I/O interrupts are masked while an I/O interrupt is processed. External interrupts and I/O interrupts are masked when either type is being processed. Machine check interrupts are masked during the processing of a machine check interrupt.

  38. Fig. 17.21: Simultaneous interrupts.

  39. Program States • The computer • problem state (application program) • supervisory state (operating system) • A given program • ready state • wait state

  40. Fig. 17.22a: Memory holds one application program.

  41. Fig. 17.22b: The program issues an SVC.

  42. Fig. 17.22c: The SVC interrupt handler begins executing.

  43. Fig. 17.22d: The interrupt handler starts the physical I/O operation.

  44. Fig. 17.22e: The SVC interrupt handler checks the channel status word.

  45. Fig. 17.22f: The program and the system (because there is only one program) are in a wait state.

  46. Fig. 17.22g: Following an I/O interrupt, the I/O interrupt handler gets control.

  47. Fig. 17.22h: The application program resumes processing.

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