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Stage III : February 9 h 2004 GATE LEVEL DESIGN

Presentation #4: Rijndael Encryption. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14). Stage III : February 9 h 2004 GATE LEVEL DESIGN. Overall Project Objective: Implement the new AES Rijndael algorithm on chip.

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Stage III : February 9 h 2004 GATE LEVEL DESIGN

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  1. Presentation #4: Rijndael Encryption Team W1Design Manager: Rebecca Miller1. Bobby Colyer (W11)2. Jeffrey Kuo (W12)3. Myron Kwai (W13)4. Shirlene Lim (W14) Stage III: February 9h 2004 GATE LEVEL DESIGN Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

  2. Status • Design Proposal • Architecture Proposal • Size Estimates/Floorplan • Gate Level Design • Schematic Design (needs to be changed) • Layout (10% done) • To be Done • Simulations/Optimizations • Everything else… 18-525 Integrated Circuit Design Project

  3. Design Decisions & Problems • DECISIONS • Change Verilog to match new input control logic to SBOX • Previously using MUX, now using ANDs • Implemented clock divider using counters • Propagate valid-in signal through dffs to obtain valid-out signal • Tried adding 3rd SBOX • PROBLEMS • Transistor Count is TOO big (~45k) • Should we remove 5 rounds of permutations? (Ideal) • Should we remove the third SBOX? (More problems: Wiring & Control Logic Change) • Top Level Schematic simulations not done • All blocks simulated and working • Except output logic from SBOX (Demux logic) 18-525 Integrated Circuit Design Project

  4. FLOORPLAN 18-525 Integrated Circuit Design Project

  5. 18-525 Integrated Circuit Design Project

  6. ADDED SBOX #3 • Previous design inefficient for small text • But increased transistor count drastically to ~45k 18-525 Integrated Circuit Design Project

  7. ELIMINATION • Eliminate 5 rounds • Eliminate 1 SBOX & control logic • Reduce transistor count to 27k 18-525 Integrated Circuit Design Project

  8. FUNCTIONAL MODEL OF ROM module logicandsbox (Out, In); output [7:0] Out; input [7:0] In; reg [7:0] Out; always @(In) case(In) // synopsys full_case parallel_case 8'h00: Out=8'h63; 8'h01: Out=8'h7c; 8'h02: Out=8'h77; 8'h03: Out=8'h7b; 8'h04: Out=8'hf2; 8'h05: Out=8'h6b; 8'h06: Out=8'h6f; 8'h07: Out=8'hc5; 8'h08: Out=8'h30; 8'h09: Out=8'h01; 8'h0a: Out=8'h67; 8'h0b: Out=8'h2b; 8'h0c: Out=8'hfe; 8'h0d: Out=8'hd7; 8'h0e: Out=8'hab; Case Statements 18-525 Integrated Circuit Design Project

  9. Schematic Simulation Results e0 34 e7 8b 18-525 Integrated Circuit Design Project

  10. Metal Directionality 18-525 Integrated Circuit Design Project

  11. PREVIOUS AREA ESTIMATE 18-525 Integrated Circuit Design Project

  12. Previous Transistor Count(Assuming 32-bit Implementation) • XORs 14,336 • DFFs 6,416 • ANDs 120 • SBOX 2304 • Muxes & Demuxes 1074 • Buffers (10%) 2000 Total: 26,250 18-525 Integrated Circuit Design Project

  13. Current PROBLEMATIC Transistor Count(Assuming 32-bit Implementation) • Clock Divider ~210 • Text In ~362 • Valid signals ~304 • Input Logic (3) ~7320 • Logic & SBOX (3) ~8916 • Output Logic (3) ~10,944 • Final Text Output ~256 • Pipeline DFFs ~4608 • Key Expansion (10) ~3840 • Round Permutations (9) ~8280 Total: ~45040 18-525 Integrated Circuit Design Project

  14. Alternative ImplementationsTransistor Count(Assuming 32-bit Implementation) • Current ~45,040 • Minus 1 SBOX & Logic ~35,980 • Minus 5 rounds & 1 SBOX and logic ~27,156 • Problems: • Deciding between the three implementations • Security problems, transistor counts, • Pipelining implementation given consideration 18-525 Integrated Circuit Design Project

  15. Questions?Answers??? 18-525 Integrated Circuit Design Project

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