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Chapters 9 & 10 Peripheral Programming & Exceptions And Interrupts

Chapters 9 & 10 Peripheral Programming & Exceptions And Interrupts. Peripheral Programming. Peripheral programming is one of the most important reasons for studying assembly language. Implementing device drivers as interface between programs and I/O devices Three strategies

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Chapters 9 & 10 Peripheral Programming & Exceptions And Interrupts

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  1. Chapters 9 & 10Peripheral Programming&Exceptions And Interrupts

  2. Peripheral Programming Peripheral programming is one of the most important reasons for studying assembly language. Implementing device drivers as interface between programs and I/O devices Three strategies (programmed) polled I/O interrupt-driven I/O direct memory access (DMA)

  3. Programmed I/O No special instructions for I/O Memory-mapped I/O: I/O port is treated exactly like a memory location. Some I/O ports have more than one internal locations: treated like a block of memory locations

  4. 0000 Address Bus 0400 Data Bus Program 2000 Data I/O Memory CPU 8000 I/O Memory-mapped I/O 8003

  5. Programmed I/O * Transmit 256 bytes to display OutPort EQU $8001 DataBlk EQU $2000 Size EQU 256 LEA DataBlk,A0 MOVE.W #Size-1,D0 Again MOVE.B (A0)+,OutPort DBRA D0,Again The following program does not work. The I/O operation is much slower than CPU execution!  Data will be lost  Flow control needed DBRA Dn,Label RTL Def.: [Dn]  [Dn]-1 IF [Dn]  -1 THEN [PC]  Label

  6. Memory 8000 8002 RDY ERR Programmed I/O - Polling The I/O port includes 2 registers: data register and status register. The data register is used to transfer the data. The status register tells CPU if the data register is ready. 0 8 7 15

  7. OutPort EQU $8001 Status EQU OutPort+2 DataBlk EQU $2000 ERR EQU 0 RDY EQU 7 Size EQU 256 LEA DataBlk,A0 MOVE.W #Size-1,D0 Again BTST #RDY,Status BEQ Again BTST #ERR,Status BNE Error MOVE.B (A0)+,OutPort DBRA D0,Again : Error Programmed (Polled) I/O The polling loop is the waste of CPU time.

  8. Interrupt-driven I/O No polling loop. The I/O can request service from the CPU by interrupting the CPU. The CPU responds to the interrupt by executing interrupt handling routine. The CPU returns from interrupt handling routine to the former execution.

  9. Program Flow of Interrupt

  10. Priority Decoder ... IACK encoder ... IRQ IACK I/O Interrupt-driven I/O IRQ1 IPL0 IPL1 IPL2 IRQ7 FC0 IACK1 FC1 FC2 A0 IACK7 A1 A1 CPU Memory Address Bus Data Bus

  11. Interrupt-driven I/O IRQ: Interrupt request line, from I/O to CPU. IACK: Interrupt acknowledge, from CPU to I/O when CPU is ready to serve interrupt. After I/O receives IACK, it provides the CPU with the interrupt vector number (IVR) to tell CPU where the interrupt handling routine is. The CPU pushes the current PC and the status registers onto the stack. The CPU branches to the interrupt handling routine by loading PC with the interrupt vector.

  12. Difference between a subroutine and an interrupt request • Invocation • Subroutine: The programmer explicitly uses BSR to branch to a subroutine • Interrupt request: An external device, such as I/O, uses hardware signal to interrupt the CPU, and then uses IVR to tell CPU where the interrupt handling routine is • Return • Subroutine: RTS to return to caller • Interrupt: RTE to return to normal execution.

  13. OutPort EQU $8001 Status EQU OutPort+2 IVR EQU OutPort+4 DataBlk EQU $2000 RDY EQU 7 INT EQU 1 Enable EQU 2 SetUp MOVE.B #VecNum,IVR LEA DataBlk,A0 BSET #Enable,Status RTS Again MOVE.B Status,D0 BTST #INT,D0 BEQ Exit BTST #RDY,D0 BEQ Exit MOVE.B (A0)+,OutPort Exit RTE Interrupt-Driven I/O

  14. Direct Memory Access How does the CPU transfer a block of data to a peripheral? Point to source of data REPEAT Read a byte of data Transfer it to the peripheral Point to next data location UNTIL All data has been transferred Is memory-mapped I/O or interrupt-driven I/O good for this task?

  15. Direct Memory Access Interrupt-driven I/O is slow, since a von Neumann machine usually requires two accesses per instruction. One access to read the instruction and one to access the operand (data). To transfer a block of data, the direct memory access (DMA) is faster. Under DMA, the I/O transfer the data directly to or from memory without the intervention of the CPU.

  16. Data transfer using DMA 1) The CPU sets up the DMA controller by telling DMA controller - the amount of data needs transfer. - transferred to (read) or from (write) memory - where the data transferred to/from in the memory 2) The CPU releases the control of the data bus and the address bus to the DMA controller (cycle stealing). 3) The DMA controller starts transfer of one data unit when the data unit is ready. 4) After the DMA controller completes the transfer, it releases the control of data and address buses to the CPU. 5) If there are more data, go to step 2) 6) The DMA interrupts CPU to signal the completion of data

  17. Exceptions The CPU operates in one of two states: user or supervisor. The OS is running in the supervisor mode; User’s program is running in the user mode. Each state has different stack pointer: SSP and USP. Exceptions are calls to the operating system.

  18. Exception Table There are different types of exception. Each type of exception has its exception handler. Exception handler is a program, the program is part of operating system. An exception vector table contains the address of all exception handlers. When there is an exception from the user program, the CPU is forced to operate in its supervisor mode. Based on the type of exception, the OS finds out the address of exception handler from the table.

  19. To serve the interrupt, the CPU will 1) complete its current instruction. 2) save the contents of the PC on the stack. 3) save the state of the CPU on the stack. 4) get the location of interrupt handling routine. 5) jump to the interrupt handling routine. Interrupts and Exception Interrupt is a specific instance of the exception. When an interrupt occurs, the CPU decides whether to service it. The time between the CPU receiving an interrupt and time at which it responds is the interrupt latency.

  20. Instruction Cycle with Interrupts

  21. Simple InterruptProcessing

  22. Interrupts and Exception Nonmaskable interrupts: This interrupt can not be deferred and must be served. (e.g. power off) Prioritized interrupts: Each interrupt has a predefined priority, a new interrupt with lower priority can not interrupt the current interrupt handling. Vectored Interrupts: After the I/O receives IACK from the CPU, it can identify itself by providing CPU with location of interrupt handling routine.

  23. Multiple Interrupts - Sequential

  24. Multiple Interrupts - Nested

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