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Bridging the gap between asynchronous design and designers

Bridging the gap between asynchronous design and designers. Part II: Logic synthesis from concurrent specifications. Outline. Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Review of some advanced topics.

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Bridging the gap between asynchronous design and designers

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  1. Bridging the gap between asynchronous designand designers Part II: Logic synthesis fromconcurrent specifications

  2. Outline • Overview of the synthesis flow • Specification • State graph and next-state functions • State encoding • Implementability conditions • Review of some advanced topics

  3. Book and synthesis tool • J. Cortadella, M. Kishinevsky, A. Kondratyev,L. Lavagno and A. Yakovlev,Logic synthesis for asynchronouscontrollers and interfaces,Springer-Verlag, 2002 • petrify:http://www.lsi.upc.es/~petrify

  4. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  5. Specification x x y y z z z+ x- x+ y+ z- y- Signal Transition Graph (STG) (Petri Net with interpreted events (often free-choice))

  6. x y z z+ x- x+ y+ z- y- Token flow

  7. xyz 000 x+ 100 y+ z+ z+ x- 110 101 x- x+ y+ z- y- y+ z+ 001 111 y- y+ x- 011 z- 010 State graph

  8. xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Next-state functions

  9. Gate netlist x y z

  10. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  11. Bus Data Transceiver DSr LDS Device D LDTACK DSr LDS VME Bus Controller DSw LDTACK D DTACK DTACK Read Cycle VME bus

  12. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  13. LDTACK- DTACK- DTACK- LDTACK- LDS- LDS- Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ LDTACK+ DTACK+ D- DSr- DTACK+ D- DSw-

  14. DTACK- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles

  15. Circuitsynthesis • Goal: • Derive a hazard-free circuitunder a given delay model andmode of operation

  16. Speed independence • Delay model • Unbounded gate / environment delays • Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: • Consistency • Complete State Coding • Persistency

  17. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  18. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  19. LDS + LDS = 0 LDS - LDS = 1 Binary encoding of signals DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  20. 01100 00110 Binary encoding of signals 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D)

  21. ER (LDS+) LDS+ QR (LDS-) LDS- LDS- LDS- ER (LDS-) QR (LDS+) Excitation / Quiescent Regions

  22. LDS+ LDS- LDS- LDS- Next-state function 0  1 0  0 1  1 1  0

  23. Next-state function. Exercise A+ B+ C+ A- B- C-

  24. LDS+ LDS- LDS- LDS- 10110 10110 Next-state function 0  1 0  0 1  1 1  0

  25. DTACK DSr DTACK DSr D LDTACK D LDTACK 00 00 01 01 11 11 10 10 00 00 01 01 11 11 10 10 Karnaugh map for LDS LDS = 1 LDS = 0 - - - 0 0 - 1 1 - - - - - - - - 1 1 1 - - - - - 0 0 - 0 0 0 - 0/1?

  26. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  27. DSr+ DSr+ DSr+ Concurrency reduction LDS+ LDS- LDS- LDS- 10110 10110

  28. Concurrency reduction DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS-

  29. State encoding conflicts LDS+ LDTACK- LDS- LDTACK+ 10110 10110

  30. CSC+ CSC- Signal Insertion LDS+ LDTACK- LDS- LDTACK+ 101101 101100 D- DSr-

  31. a a a a a a Regions and excitation regions • Region = set of states r s.t. each event a either enters, or exits or does not cross it (Nielsen et el. 92) • Pre-region: a exits r • Post-region: a enters r • Excitation region: all states exited by a • Any region is a union of minimal regions a a enter exit non-cross excitation region

  32. Event insertion (Vanbekbergen ‘92) a b c delay exit transitions by x ER(x) SR(x) S - ER(x) b a x x x x b c ER(x) S - ER(x)

  33. a b b a Event insertion (Vanbekbergen ‘92) • Properties to preserve during insertion: • trace equivalence • speed-independence necessary and sufficient conditions: • persistency (Speed-Independence Preserving set) • commutativity a b b a

  34. Regions and SIP sets • Legal SIP set: • region • persistent excitation region • exit border of persistent region • intersection of pre-regions (if forward connected)

  35. State signal insertion (Vanbekbergen ‘92) • S+ (ER(x+)) and S- (ER(x-)) must be SIP (speed-independence) • I-partition must not have illegal arcs (well-formedness) e.g. S0 è S1, S+ è S0, S1 è S+ are illegal S0 S0 x+ x- S+ S- S+ S- S1 S1

  36. x+ y+ x+ y+ x- y- x- y- y- x- y- x- y+ x+ y+ x+ x+ y+ x- y- y- x- y+ x+ Using regions to find bipartitions • Bricks: • minimal regions • intersections of pre-regions and post-regions • Blocks = È bricks (r1 Ç r2)È(r3 Ç r4)

  37. From bipartition to I-partition • Find a bipartition {b, b} • Find (by expansion) exit borders which are well-formed and SIP • Add the new state signal z 100 010 x+ y+ x+ y+ x+ y+ x- y- x- y- 110 z- y- x- y- x- 111 x- y- y+ x+ y+ x+ 011 101 y- x- 001 z- 000 y+ x+

  38. The cost function • Comparison among pairs of I-partitions: • correctness (SIP, well-formed, ...) • number of solved CSC conflicts • estimation of logic • Trade-off between CSC conflicts and estimated logic

  39. Conclusions • Regions guide the search among blocks of states • Regions are the base of symbolic manipulations of TSs • Property-preserving TS transformations • Completeness: all CSC conflicts are solvable for excitation-closed TSs • Designer/tool interaction made easier by STG è TS è STG transformations • Public domain PN and asynchronous circuit synthesis tool Petrify: http://www.ac.upc.es/~vlsi/petrify/petrify.html

  40. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  41. Complex-gate implementation

  42. Implementability conditions • Boundedness (reachability space is finite) • Consistency • Rising and falling transitions of each signal alternate in any trace • Complete state coding (CSC) • Next-state functions correctly defined • Persistency • No event can be disabled by another event (unless they are both inputs)

  43. a- c+ a 100 000 001 b c b+ b+ Persistency a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

  44. Implementability conditions • Bound + Consistent + CSC + Persistent • There exists a speed-independent circuit that implements the behavior of the STG(under the assumption that any Boolean function can be implemented with one complex gate)

  45. Implementability analysis • Boundedness (reachability graph with markings) • Consistency (concurrency + alternation) Polynomial for free-choice • Persistency (conflicts) Polynomial for free-choice • CSC (requires SG extraction) Implementability analysis is not hard

  46. Part3. Advanced topics • Logic Decomposition • Optimization based on timing information

  47. a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ d- d+ 0111 a+ a+ 1111 b- b- 1011 a- c- a- c- 0011 1001 a- c- d- 0001

  48. ab 0000 cd 00 01 11 10 a+ 1000 0 0 0 0 00 b+ 1100 1 0 a- 01 0100 c+ 1 1 1 1 0110 11 d- d+ 0111 1 10 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ER(d+) ER(d-)

  49. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 Complex gate

  50. S z C R Implementation with C elements • • •  S+  z+  S-  R+  z-  R-  • • • • S (set) and R (reset) must be mutually exclusive • S must cover ER(z+) and must not intersect ER(z-)  QR(z-) • R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

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