1 / 24

A CMOS Low Power Current-Mode Polyphase Filter

King Fahd University of Petroleum & Minerals KFUPM, Department of Electrical Engineering. A CMOS Low Power Current-Mode Polyphase Filter. By Hussain Alzaher & Noman Tasadduq. OUTLINE. INTRODUCTION Bluetooth receiver Available solutions PROPOSED APPROACH CURRENT AMPLIFIER Introduction

cooper-cruz
Download Presentation

A CMOS Low Power Current-Mode Polyphase Filter

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. King Fahd University of Petroleum & Minerals KFUPM, Department of Electrical Engineering A CMOS Low Power Current-Mode Polyphase Filter By Hussain Alzaher & Noman Tasadduq

  2. OUTLINE • INTRODUCTION • Bluetooth receiver • Available solutions • PROPOSED APPROACH • CURRENT AMPLIFIER • Introduction • Fully differential current amplifier (FDCA) • BASIC PRINCIPLE • PROPOSED FILTER • Single ended realization • Fully differential realization • EXPERIMENTAL RESULTS • COMPARISON WITH THE LITERATURE • CONCLUSION

  3. INTRODUCTION • Low-IF Receiver Architecture • Unlike zero-IF: Low-IF = No DC offset and flicker noise problems • Image problem • Solution: Polyphase bandpass filter

  4. INTRODUCTION Available Solutions • Active-RC filters. • High dynamic range. • Limited bandwidth. • Relatively high power consumption. • gm-C filters • High frequency. • Programmable. • Poor linearity=Limited dynamic range.

  5. PROPOSED APPROACH • Design new polyphase filter based on optimum active element • Higher bandwidth than op-amp  lower power • Better linearity than gm  better DR

  6. PROPOSED APPROACH • Current-mode processing inherently possess • High BW + Low voltage  Low Power • High signal swing  High linearity • Current Amplifier based Filter • Simple filter topology  Low power

  7. CURRENT AMPLIFIER (CA) Introduction • Conveys input current from a low impedance input terminal (X) to a high impedance output terminal (Z). • Gain=K, (sizing of current mirror transistors). • Two types: positive CA (input and output currents are both going in the same direction) and negative CA (having currents in opposite directions). CA with +ve output CA with -ve output

  8. CURRENT AMPLIFIER (CA) Single Input/Dual Output CA Core Input Stage Current Mirrors Class-AB Output Stage

  9. CURRENT AMPLIFIER (CA) Four terminal device, with two input and two output currents. Fully Differential Current Amplifier (FDCA) (Ideally common mode gain is zero) Details available in: H. Alzaher, N. Tasadduq, “Realizations of CMOS fully differential current followers/amplifiers," IEEE International Symposium on Circuits and Systems (ISCAS 2009), pp. 1381-1384.

  10. BASIC PRINCIPLE • General Transfer function • Image Rejection

  11. BASIC PRINCIPLE • Systematic Design • Lowpass filter can be converted to a bandpass polyphase filter centered at ωc. • Complex poles are achieved by using cross-coupling between I and Q paths.

  12. PROPOSED FILTER • Single Ended Realization Simple LP filter to complex filter • Independent control ofωcwithout changing Q using R and/or C.

  13. PROPOSED FILTER • Nominal Values • 6th order polyphase filter is implemented. • The nominal center frequency of 3MHz and overall bandwidth of 1MHz are achieved by selecting R1=13kW, C1=8.5pF and K2=2.1. • K1 is 1 to achieve a gain of unity.

  14. FDCA FDCA PROPOSED FILTER • Fully Differential Realization

  15. PROPOSED FILTER FDCA with four outputs

  16. FOUR OUTPUT CA REALIZATION Core biasing circuit of IB=9mA and ISB=3mA is shared for all FDCA Total biasing current is

  17. EXPERIMENTAL RESULTS • Standard 0.18mm CMOS process. • Supply Voltage ±1.35V. • Total Supply Current 0.88mA. • Center frequency 3MHz. • Bandwidth 1MHz. • Center frequency tuning using capacitor arrays.

  18. EXPERIMENTAL RESULTS • Signal magnitude response showing center frequency tuning

  19. EXPERIMENTAL RESULTS

  20. COMPARISON WITH LITERATURE • B. Shi, W. Shan, and P. Andreani, 2002, “A 57dB image band rejection CMOS gm-C polyphase filter with automatic frequency tuning for Bluetooth,” Proc. Int. Symp. Circuits and Systems, ISCAS’ 2002., vol. 5, pp. V-169 - II-172, 2002. • A. Emira, and E. Sánchez-Sinencio, “A pseudo differential complex filter for Bluetooth with frequency tuning,” IEEE Trans. Circuits and Syst.-II, vol. 50, pp. 742 – 754, October 2003. • B. Guthrie, J. Hughes, T. Sayers, and A. Spencer, “A CMOS gyrator Low-IF filter for a dual-mode Bluetooth/ZigBee transceiver,” IEEE J. Solid-State Circuits, vol. 55, no. 9, pp. 1872-1878, Sep. 2005. • C. Psychalinos, “Low-voltage log-domain complex filters,” IEEE Trans. Circuits and Syst.-II, vol. 55, no. 11, pp. 3404- 3412, Dec. 2008.

  21. COMPARISON WITH LITERATURE

  22. COMPARISON RESULTS • Power consumption/pole • Proposed filter and [3] • Image rejection • Propsed filter and [2] • SFDR • Proposed filter

  23. CONCLUSION • CA based filters inherently exhibit higher bandwidth than active-RC and better linearity than gm-C. • This is demonstrated by a new polyphase filter with improved SFDR and IRR while using relatively lower power.

  24. Thank You,

More Related