1 / 12

Microprocessor Design Multi-cycle Datapath

Microprocessor Design Multi-cycle Datapath. Nia S. Bradley Vijay. Datapath. PCSource. PCWrite etc. Shift left 2. 26-31 to Control FSM. 0-25. RegWrite. 21-25. 28-31. 16-20. Instr. reg. (IR). A Reg. PC. Addr. Memory. ALU. Register file. ALUSrcA=1. CC3. ALUSrcB=00.

cora-moses
Download Presentation

Microprocessor Design Multi-cycle Datapath

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Microprocessor DesignMulti-cycle Datapath Nia S. Bradley Vijay

  2. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  3. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  4. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  5. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  6. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  7. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  8. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  9. Control FSM Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Start State 0 1 lw or sw J R B 3 2 lw 6 8 9 sw 4 5 7 Fall 2010, Sep 15 . . . 9 ELEC 5200-001/6200-001 Lecture 5

  10. Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite 0-5

  11. Problems & Concerns • During simulation processor goes into a loop when fetching a new instruction

  12. Next Steps • Implementation on FPGA board

More Related