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EE 166 Design Project

EE 166 Design Project. 4 – Bit Magnitude Comparator. Design By Man Hong Liu Kee-Hoon Choi Tak Chuen Wong. Diagram of 4-Bit Comparator. A3. A2. A1. A0. B3. B2. B1. B0. 4 – Bit Magnitude Comparator. GT. EQ. LT. Specification. Power : Less than 0.25 W Frequency : 200 MHz

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EE 166 Design Project

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  1. EE 166 Design Project 4 – Bit Magnitude Comparator Design By Man Hong Liu Kee-Hoon Choi Tak Chuen Wong

  2. Diagram of 4-Bit Comparator A3 A2 A1 A0 B3 B2 B1 B0 4 – Bit Magnitude Comparator GT EQ LT

  3. Specification Power : Less than 0.25 W Frequency : 200 MHz AMI06 Technology

  4. Method • Used Velilog to verify our logic • Hand Calculation to determine approx. delay time and speed. • Completed all the logic gate: AND, XNOR, NAND, Inverter (transistor size, simulation) • Integrated all parts (Modification if needed) • Layout (Modification if needed) • Extracted Simulation

  5. Sub – Systems of our Design • Three Sub-Systems a. Equal Module (A = B) b. Less than Module (A < B) c. Greater than Module (A > B)

  6. Equal Module Output high when two inputs equal (A = B) Four 2-input XNOR Gate One 4-input NAND Gate

  7. Less Than Module Output high when input A is less than input B. (A < B) Three Inverters Five 2-input NAND Gates One 3-input NAND Gate Two 4-input NAND Gates Three signal from EQ module (EQ3, EQ2, EQ1)

  8. Greater Than Module Output high when input A is greater than input B. (A > B) Three Inverters Five 2-input NAND Gates One 3-input NAND Gate Two 4-input NAND Gates Three signal from EQ module (EQ3, EQ2, EQ1)

  9. Full Schematic

  10. Schematic of 2 Input XNOR Gate

  11. Schematic of Equal Module

  12. Schematic of LT Module

  13. Schematic of GT Module

  14. Schematic of 4-bit Comparator

  15. 4-bit Comparator Test Bench Connection

  16. Transient Response

  17. Transient Response A3 < B3 A = B A3 > B3

  18. Power

  19. Results Power : Approx. 0.26 mW (within 5 %) Time Delay : 830 ps for EQ module Good !!! We met our specification

  20. Layout of 2-Input XNOR Gate

  21. Layout of Equal Module

  22. Layout of LT Module

  23. Layout of GT Module

  24. Layout of 4-bit Comparator

  25. Extracted View of 4-bit Comparator

  26. LVS Reports

  27. Extracted Transient Response

  28. Extracted Power Measure

  29. Results Power : Approx. 0.20 mW (within 5 %) Time Delay : EQ Module = 810 ps (LT & GT are faster than EQ) Good !!! We met our specification

  30. Conclusion Problem : Too much Power consumption. Solution : We simplified our logic. We deleted some of inverters. Result : Power goes down.

  31. Initial Full Schematic

  32. Final Full Schematic

  33. Conclusion Better result from layout than schematic After all, our design works !!!

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