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RF2TTC Review May 2006

RF2TTC Review May 2006. Receiver Crate Functionalities Design AOB. RECEIVER CRATE [Overview]. RECEIVER CRATE [Location]. Magnetic field: <100gauss Radiations: Total dose: 1.4 rad/10yrs Ch Hadrons >20MeV fluency: 1.5 10 6 /10yrs/cm -2 Neutrons>20MeV: 3.1 10 6 /10yrs/cm -2.

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RF2TTC Review May 2006

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  1. RF2TTC ReviewMay 2006 TTC meeting, 2nd of May 2006

  2. Receiver Crate • Functionalities • Design • AOB TTC meeting, 2nd of May 2006

  3. RECEIVER CRATE [Overview] TTC meeting, 2nd of May 2006

  4. RECEIVER CRATE [Location] Magnetic field: <100gauss Radiations: Total dose: 1.4 rad/10yrs Ch Hadrons >20MeV fluency: 1.5 106/10yrs/cm-2 Neutrons>20MeV: 3.1 106/10yrs/cm-2 TTClab (build 4) TTC meeting, 2nd of May 2006

  5. RECEIVER CRATE [Crates] • ATLAS, CMS, LHCb: • 1 LHC standard 6U VME crate per experiment • Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A) • ALICE: • 1 ALICE Trigger standard 6U VME crate (water cooled) • Power supply type changed from 0P17.0711 to 0P17.0701(+3.3V/100A, +5V/100A, +/-12V/10A) • TTC lab: • 1 LHC standard 6U VME crate per experiment • Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A) • RF: • Use VME64 crates (no P3V3). • RF2TTC and fanout modules use +3V3, +5V and +-12V • RF_Tx and RF_Rx use only +5V and +-12V TTC meeting, 2nd of May 2006

  6. RECEIVER CRATE [Crate Controllers] • ALICE: • Standard VP315/317 from CCT • ATLAS: • Standard VP110 from CCT • CMS: • CAEN PCI-controller card A2818 + V2718 VME-PCI optical bridge • LHCb: • CAEN V1718 VME-USB bridge All these modules are POOL items. One of each will be reserved as from August 06. The TTClab is equipped with a VP110. TTC meeting, 2nd of May 2006

  7. RECEIVER CRATE [RF Analog Links] • Analog Modules • Transmitter module: RF_Tx_A (EDA-01331) • Receiver module: RF_Rx_A (EDA-01332) • Miteq links validated • Specs: • Freq max: 3GHz (typ) • Vin: 10dBm (max) • Vout: 10dBm (max) • Measured Phase Noise: • 400MHz -> 0.4ps (pkpk) • 40MHz -> 0.4ps (pkpk) • 10MHz -> 13ps (pkpk) More results in the evaluation report • Typical output levels: • Bunch Clock = 0dBm continuous sinewave • Orbit = 1Vpk pulse on 50 Ohms • Quantities: • 10 links have been ordered in November05 • 10 to be ordered soon => Enough to work until 2007 TTC meeting, 2nd of May 2006

  8. RECEIVER CRATE [RF Analog Links] • 6U 4TE VME (VME 64x and VME 64 compatible) • 3 internal registers • Power warning led threshold (RW) • CH1Power monitoring (Read Only) • CH2 Power monitoring (Read Only) • Manual or geographical addresses • Emi Filters on each laser power pin • FPGA programmed using VHDL/ Visual Elite to match the AB/RF requirements • Heat sink required to keep the Miteq Rx and Tx at about 35 C Deg. TTC meeting, 2nd of May 2006

  9. RECEIVER CRATE [RF Analog Links] • Power consumption: • Component price/ dual module • Some layout changes on-going • following the review done with AB/RF • PCB manufacture to begin this week TTC meeting, 2nd of May 2006

  10. RECEIVER CRATE [RF Digital Links] • Digital Modules (RF_Tx_D and RF_Rx_D) • First test boards made with PHOTON 155Mbps/TRR-1B43 pair • Performance evaluated on the same setup than the analog links • Results available in the test report • AB/RF agreed that this could be a cheaper solution for 70% of the links, including the TTC • If the final results are as good as expected, they will use this solution for these 70% and maintain the boards the same way. • Optical components identified and ordered • Photon getting obsolete • AMS components pin compatible components • Price: • Orbit, 10MHz, 40MHz: 156Mbps links • 400MHz: 1.2Gbps • Design on-going (PH/ESS). • Close to the analog boards, but higher density. TTC meeting, 2nd of May 2006

  11. RECEIVER CRATE [Client modules] Custom modules: • ATLAS CTP • TTCci • .. • To have a full compatibility with all the client modules, • The BC_out signals can be ECL AC coupled • The Orbit_out signals need to be NECL DC coupled TTC meeting, 2nd of May 2006

  12. RECEIVER CRATE [TTC Clock fanout] • TTC Clock fanout(EDA-01240-V1, PH/MIC) • Dual 1:18 ECL fanout • 4 NIM outputs per input (ALICE requirement) • 1 status led per input (presence of clock). • Maximum density • The 2 dual modules can be daisy chained. • Fully AC coupled Prototype produced • Power: 5V-5A, • Jitter: In/Out skew=8ps rms, Cy2Cy=11ps rms • Skew between outputs: a few ps Design needs to be adjusted to be ‘orbit-compliant’ (AC -> DC coupling) TTC meeting, 2nd of May 2006

  13. Receiver Crate • Functionalities • Design • AOB TTC meeting, 2nd of May 2006

  14. FUNCTIONALITIES [Inputs/Outputs] • VME 6U module • 1 slot if possible • Inputs • 3 BC inputs (SMA or Lemo00) (RF signals) • 2 Orbit inputs (RF signals) • 1 Optical input for the BST signals • Outputs (can be discussed) • 4 ECL BC outputs (BC1, BC2, BCref, MainBC) • AC coupled • 4 NIM copies • 3 NECL Orbit outputs (Orb1, Orb2, MainOrb) • DC coupled • Synchronised respectively to BC1, BC2, MainBC • 3 NIM copies • Status leds TTC meeting, 2nd of May 2006

  15. FUNCTIONALITIES [Block Diagram] Adjustable Reset possible Monitored via a VME register Status Led TTC meeting, 2nd of May 2006

  16. FUNCTIONALITIES [VME Interface] • VME Interface • D32/A32 access mode (AM 0x09) • 8 bits of board address (A31-A24) (2 rotary switches). • Geographical addresses usable if the manual address is 0x00 (reloaded at power up or by sysreset) • Interrupts are possible, but have to remain optional. They may not be handled by every types of VME controllers. TTC meeting, 2nd of May 2006

  17. FUNCTIONALITIES [Signal Adjustments] • Adjustable parameters (via VME registers) • BC1, BC2, BCref • Adjustable level on the comparator input • Multiplexing between each input and the internal 40.078MHz clock • Adjustable phase shift (steps of 0.5ns) • Main BC • Multiplexing between BC1, BC2, BCref and internal clock • Adjustable phase shift (steps of 0.5ns) • Orbit1 and Orbit2 • Adjustable level on the comparator input to match various types of signals • Adjustable phase shift before the latching with the corresponding BC • Multiplexing between each input and an internal counter • Adjustable length • Adjustable coarse delay (steps of 25ns) • Adjustable phase shift (steps of 0.5ns) before the output • Main Orbit • Multiplexing between the two orbit sources and an internal counter • Adjustable length • Adjustable coarse delay (steps of 25ns) • Adjustable phase shift (steps of 0.5ns) before the output TTC meeting, 2nd of May 2006

  18. FUNCTIONALITIES [Status & Remote Control] • Board status data • Read only registers: Orbit available, QPLL lock, TTC ready, machine mode • Leds: selected signals, QPLL lock, available orbit, VME access, VME berr, BST signal ready... • Remote control of the adjustments • Orbit comparator level/ orbit dephasing: FIFO containing the 128 last BC counts between two consecutive Orbit signals (ideally 3564 each). The content of this FIFO can indicate a bad level on the comparator, a dephasing, a wrong synchronisation. This FIFO is filled at reception of a VME command. • Clock status: QPLL status indicates if the clock is absent or if the comparator level is wrong. Would some other ways being required? • Orbit counter, 32 bits (106 hours). Could be reset, either manually, or at the beginning of a run if required TTC meeting, 2nd of May 2006

  19. FUNCTIONALITIES [Working modes] Beam Dump Beam Dump E(450GeV -> 7TeV) E(450GeV -> 7TeV) time injection ~15 min ramping ~28 min squeeze ~15 min physics ~10-20 H • Manual and automatic modes for signal selection • Manual mode: the source of each output signal is manually selected • Automatic mode: • Change the selected sources according to the machine mode • 2 types of parameters must be configured: • Which machine mode is considered to be ‘run’ (ex: ramping, adjust, collide..) or ‘no run’ (beam dump, no beam, …) • Which source for each signal must be selected during ‘run’ or ‘no run’. Example for the Main BC: Internal clock during ‘no run’ periods, and BCref during run periods • 3 different configurations can be defined for the signal selection. • Which means: • 1 register to define in which mode we are (manual, auto1, auto2, auto3) • 1 register to define which machine mode corresponds to which state • 1 register to define the sources set when ‘no run’………………… • 3 registers to define the sources set when ‘run’ (1 per auto mode)… Run/no run Automode1 Automode2 Automode3 TTC meeting, 2nd of May 2006

  20. FUNCTIONALITIES [State Machine] Beam Dump Beam Dump E(450GeV -> 7TeV) E(450GeV -> 7TeV) time injection ~15 min ramping ~28 min squeeze ~15 min physics ~10-20 H Run/no run Automode1 Automode2 Automode3 Manual TTC meeting, 2nd of May 2006

  21. FUNCTIONALITIES [register map -1] Bunch Clocks registers TTC meeting, 2nd of May 2006

  22. FUNCTIONALITIES [register map -2] Orbit registers TTC meeting, 2nd of May 2006

  23. FUNCTIONALITIES [register map -3] Orbit registers TTC meeting, 2nd of May 2006

  24. FUNCTIONALITIES [register map -4] BST registers TTC meeting, 2nd of May 2006

  25. FUNCTIONALITIES [register map -5] General registers TTC meeting, 2nd of May 2006

  26. FUNCTIONALITIES [register map -6] Commands TTC meeting, 2nd of May 2006

  27. Receiver Crate • Functionalities • Design • AOB TTC meeting, 2nd of May 2006

  28. DESIGN [Block Diagram] TTC meeting, 2nd of May 2006

  29. DESIGN [Technology choices] • ECL/LVDS components • LVDS 2 ECL conversion application note ECL (NECL, PECL, LVPECL) LVDS (2.5V) LVCMOS-LVTTL (3.3V) LVCMOS (2.5V) TTC meeting, 2nd of May 2006

  30. DESIGN [Schematics & Features] See schematics • Coupling considerations • Conversions • ECL2LVDS • LVDS2PECL • PECL2NIM • NECL2NIM • ECL2CMOS • BC & Orbit inputs • Coupling • Comparator choice • Voltage reference adjustment • Internal clock • Fixed oscillator • ECL differential clock lines • Orbit synchronisation process • Pulse lengthening TTC meeting, 2nd of May 2006

  31. DESIGN [Schematics & Features] See schematics • Use of CERN ASICS • Delay25 • QPLL • FPGA • Device choice • Programming modes • Signal levels • Pinout and I/o Banks • Firmware consideration • VME interface => implemented in the ATLAS TRT-TTC board • Triple logic necessary for critical registers? (working modes, auto_config) • Internal communication busses • I2C • ECL output drivers • MC100EL89 coax cable drivers TTC meeting, 2nd of May 2006

  32. DESIGN [Schematics & Features] See schematics • Power considerations • Estimation • Solutions • Debugging facilities • Test points • Spare connector • Signal tap • Bugs to be corrected • Missing pull-up resistors • PCB design • Front Panel • Layout • Prototyping • Price estimation: components about 830 $ • Quantities • Component procurement • Schedules TTC meeting, 2nd of May 2006

  33. Receiver Crate • Functionalities • Design • AOB TTC meeting, 2nd of May 2006

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