Net 321 : Computer Operating System

1. Net 321 :Computer Operating System Lecture # 8 : Main Memory part 3 Networks and Communication Department

2. Chapter 8: Main Memory

3. Non-contiguous allocation • Paging • Segmentation

4. 1. paging In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

5. 1. paging In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

6. 1. paging OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

7. 1. paging OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

8. 1. paging The OS uses a page tableto map program pages to memory frames.

9. 1. paging The OS uses a page tableto map program pages to memory frames.

10. 1. paging The OS uses a page tableto map program pages to memory frames.

11. 1. paging The OS uses a page tableto map program pages to memory frames.

12. 1. paging The OS uses a page tableto map program pages to memory frames.

13. 1. paging Paging permits a program to allocate noncontiguous blocks of memory

14. Page size (S) is defined by the hardware. Generally page size is chosen as a power of 2 such as 512 words/page or 4096 words/page etc. With this arrangement, the words in the program have an address called as logical address. Every logical address is formed of <p,d> pair 1. paging

15. Logical address: <p,d> p is page number d is displacement (offset) 1. paging

16.  When a logical address <p, d> is generated by the processor, first the frame number f corresponding to page p is determined by using the page table and then the physical address is calculated as (f*S+d) and the memory is accessed. Convert logical address to physical address in paging

17. Convert logical address to physical address in paging How to convert from logical address to physical address in paging?? Physical address = (frame # * page size) + offset

18. Convert logical address to physical address in paging

19. Example 1 n=2 and m=4 32-byte memory and 4-byte pages

20. Example 1 cont. • Consider the memory in previous figure. • Using a page size of 4 bytes and a physical memory of 32 bytes (8 frames). It is shown that how the user's view of memory can be mapped into physical memory. • Logical address 0 is page 0 ,offset 0. Indexing into the page table, we find that page 0 is in frame 5. Thus, logical address 0 maps to physical address 20 (= (5 x 4) + 0). • Logical address 3 (page 0, offset 3) maps to physical address 23 (= (5 x 4) + 3). • Logical address 4 is page 1, offset 0; according to the page table, page 1 is mapped to frame 6. Thus, logical address 4 maps to physical address 24 (= (6 x 4) + 0). • Logical address 13is page 3 ,offset 2 maps to physical address 9.

21. Important note • When we use a paging scheme, we have no external fragmentation: • Any free frame can be allocated to a process that needs it. • However, we may have some internal fragmentation. • Notice that frames are allocated as units. If the memory requirements of a process do not happen to coincide with page boundaries, the last frame allocated may not be completely full. For example, • if page size is 2,048 bytes, a process of 72,766 bytes would need 35 pages plus 1,086 bytes. • It would be allocated 36 frames, resulting in an internal fragmentation of 2,048 - 1,086 = 962 bytes. • In the worst case, a process would need  pages plus 1 byte. It would be allocated  frames, resulting in an internal fragmentation of almost an entire frame.

22. Paging Arithmetic laws Paging Arithmetic laws : • Page size = frame size = ( where n is the # of bits in offset part) • Logical address frame apace ( size )= (where m the # of bits in logical address) • Logical address frame apace ( size )= # of pages x page size • Physical address frame apace ( size )= (where x is the number of bits in physical address) • Physical address frame apace ( size)= # of fames x frame size • # of pages = • # of entries (records) in page table = # of pages

23. Example ( 8.19 at textbook) • Assuming a 1-KB page size , What are the page numbers and offsets for the following address references (provided as decimal numbers) a. 2375 b. 19366 c. 30000 d. 256

24. Example ( 8.19 at textbook) cont. Answer: Page size =2n =1024 B= 210 B # of bits in offset part (n) =10 Solution steps : Convert logical address: Decimal Binary Split binary address to 2 parts (page # , Offset), offset : n digits Convert offset & page# : Binary Decimal

25. Example ( 8.19 at textbook) cont.

26. Example (8.14 at textbook) Consider a logical address space of 64 pages of 1024 words each, mapped onto a physical memory of 32 frames. a) How many bits are there in the logical address? b) How many bits are there in the physical address? a) Method1: m =??? Size of logical address space = 2m = # of pages × page size 2m = 64 × 1024 2m = 26 × 210 2m =216 »» m=16 bit

27. Example (8.14 at textbook) cont. Method2: m =??? # of pages = 2m-n n =??? Page size=2n 1024=2n 210=2n »» n=10 bit Again: # of pages = 2m-n 64=2m-10 26=2m-10 6= m-10 »» m=16 bit

28. Example (8.14 at textbook) b) Let (x) is number of bits in the physical address x =??? Size of physical address space = 2x Size of physical address space = # of frames × frame size (frame size = page size ) Size of physical address space = 32 × 1024 2x =25 × 210 2x = 215 »» number of required bits in the physical address=x =15 bit

29. Example (8.22 at textbook) Consider a logical address space of 32 pages of 1024 words per page, mapped onto a physical memory of 16 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address? a) m =??? Size of logical address space = 2m = # of pages × page size = 32 × 1024 = 215 »» m=15 bit

30. Example (8.22 at textbook) cont. b) Size of physical address space = # of frames × frame size (frame size = page size ) Size of physical address space = 16 × 1024 = 214 »» number of required bits in the physical address =14 bit

31. Page Table implementation Every access to memory should go through the page table. Therefore, it must be implemented in an efficient way. How to Implement The Page Table? Using fast dedicated registers Keep the page table in main memory Use content-addressable associative registers

32. Keep page table in fast dedicated registers. Only the OS is able to modify these registers. However, if the page table is large, this method becomes very expensive since requires too many registers. Given a logical address to access the word in physical memory, first access the page table stored in registers, which requires register access time (rat), and then find out the physical address and access the physical memory, which requires memory access time (mat). Therefore effective memory access time (emat) becomes: emat= rat + mat 1.Using fast dedicated registers

33. 1.Using fast dedicated registers p d PTLR: Page Table Length Register logical address physical address access Page Table in registers access memory f d P<PTLR rat mat YES NO ERROR Effective Memory Access Time emat=rat+mat

34. In this second method, the OS keeps a page table in the memory, instead of registers. For every logical memory reference, two memory accesses are required: To access the page table in the memory, in order to find the corresponding frame number. To access the memory word in that frame This is cheap but a time consuming method. Therefore effective memory access time (emat) becomes: emat= 2 * mat 2.Keep the page table in main memory

35. 2.Keep the page table in main memory logical address p d PTBR: Page Table Base Register PTLR: Page Table Length Register Access page tableentry in Memory at address PTBR + p physical address P<PTLR YES access memory f d NO mat mat ERROR Effective Memory Access Time: emat=mat+mat=2mat

36. This is a mixing of first two methods. Associative registers are small, high speed registers built in a special way so that they permit an associative search over their contents. That is, all registers may be searched in one machine cycle simultaneously. However, associative registers are quite expensive. So, a small number of them should be used. In the overall, the method is not-expensive and not-slow. 3.Use content-addressable associative registers

37. 3.Use content-addressable associative registers • When a logical memory reference is made, first the corresponding page number is searched in associative registers. • If that page number is found in one associative register (hit) then the corresponding frame number is get • else (miss) the page table in memory is accessed to find the frame number and that <page number, frame number> pair is stored into associative registers. Once the frame number is obtained, the memory word is accessed. • The hit ratio is defined as the percentage of times that a page number is found in associative registers. • Hit ratio is important in performance of the system since it affects the effective memory access time. In the case of finding the page number in associative registers, onlyone memory access time is required whereas if it cannot be found two memory accesses are needed. So, greater the hit ratio, smaller the effective memory access time.

38. 3.Use content-addressable associative registers • Effective memory access time is calculated as fallows: emat= h *ematHIT + (1-h) * ematMISS where h = The hit ratio ematHIT = effective memory access time when there is a hit = rat + mat ematMISS = effective memory access time when there is a miss = rat + mat + mat

39. 3.Use content-addressable associative registers physical address logical address Found? p d Access PT entry in Memory at address PTBR + p Yes (HIT) physical address No (MISS) P<PTLR Yes access memory search PT in AR f d f d rat No mat mat ERROR Effective Memory Access Time: h: hit ratio Emat=h *ematHIT + (1-h) * ematMISS =h(rat+mat)+(1-h)(rat+mat+mat)

40. Example Assume we have a paging system which uses associative registers. These associative registers have an access time of 30 ns, and the memory access time is 470 ns. The system has a hit ratio of 90 %. rat=30 ns mat=470 ns h=0.9 3زUse content-addressable associative registers

41. rat=30 ns, mat=470ms, h=0.9 Now, if the page number is found in one of the associative registers, then the effective access time: ematHIT = 30 + 470 = 500 ns. Because one access to associative registers and one access to the main memory is sufficient. Use content-addressable associative registers

42. rat=30 ns, mat=470ns, h=0.9 On the other hand, if the page number is not found in associative registers, then the effective access time: ematMISS = 30 + (470+470) = 970 ns. Since one access to associative registers and two accesses to the main memory are required. Use content-addressable associative registers

43. rat=30 ns, mat=470ns, h=0.9 ematHIT = 500 ns, ematMISS = 970 ns. Then, the emat is calculated as follows: emat= h *ematHIT+ (1-h) * ematMISS = 0.9 * 500 + 0.1 * 970 = 450 + 97 = 547 ns Use content-addressable associative registers

44. Example ( 8.10 at textboox) • Consider a paging system with the page table stored in memory. a. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? b. If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.)

45. Example ( 8.10 at textboox) cont. Answer: a. memory reference time= 200+200= 400 ns ( 200 ns to access the page table in RAM and 200 ns to access the word in memory) b. Case (1) :page entry found in associative registers (part1) Memory access time = 0+200=200 ns ( 0 ns to access the page table in associative registers and 200 ns to access the word in memory) Case (2) :page entry NOT found in associative registers (part1) but found in page table in RAM Memory access time = 0+200+200=200 ns ( 0 ns to access the page table in associative registers (part1) ,200 ns to access the page table(part2) in RAM and 200 ns to access the word in memory) Effective access time =emat= h *ematHIT + (1-h) * ematMISS Effective access time = [0.75 × 200 ]+ [0.25 × 400]= 250 ns.

46. Sharing pages is possible in a paging system, and is an important advantage of paging. It is possible to share system procedures or programs, user procedures or programs, and possibly data area. Sharing pages is especially advantageous in time-sharing systems. Sharing Pages

47. A reentrant program (non-self-modifying code = read only) never changes during execution. So, more than one process can execute the same code at the same time. Each process will have its own data storage and its own copy of registers to hold the data for its own execution of the shared program. Sharing Pages

48. Example 3.4 Consider a system having page size=30 MB. There are 3 users executing an editor program which is 90 MB (3 pages) in size, with a 30 MB (1 page) data space. To support these 3 users, the OS must allocate 3 * (90+30) = 360 MB space. However, if the editor program is reentrant (non-self-modifying code = read only), then it can be shared among the users, and only one copy of the editor program is sufficient. Therefore, only 90 +( 30 * 3 )= 180 MB of memory space is enough for this case Sharing Pages