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UNIT-II Stick Diagrams

Stick Diagrams. UNIT-II Stick Diagrams. Stick Diagrams. Stick Diagrams. N+. N+. Stick Diagrams. V DD. V DD. X. X. X. X. Gnd. Gnd. Stick Diagrams. Stick Diagram. Stick Diagrams. V DD. V DD. X. X. X. X. Gnd. Gnd. Stick Diagrams. Stick Diagrams. Stick Diagrams.

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UNIT-II Stick Diagrams

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  1. Stick Diagrams UNIT-IIStick Diagrams

  2. Stick Diagrams Stick Diagrams N+ N+

  3. Stick Diagrams VDD VDD X X X X Gnd Gnd Stick Diagrams Stick Diagram

  4. Stick Diagrams VDD VDD X X X X Gnd Gnd Stick Diagrams

  5. Stick Diagrams Stick Diagrams • VLSI design aims to translate circuit concepts onto silicon. • stick diagrams are a means of capturing topography and layer information using simple diagrams. • Stick diagrams convey layer information through colour codes (or monochrome encoding). • Acts as an interface between symbolic circuit and the actual layout.

  6. Stick Diagrams Stick Diagrams • Does show all components/vias. • It shows relative placement of components. • Goes one step closer to the layout • Helps plan the layout and routing A stick diagram is a cartoon of a layout.

  7. Stick Diagrams Stick Diagrams • Does not show • Exact placement of components • Transistor sizes • Wire lengths, wire widths, tub boundaries. • Any other low level details such as parasitics..

  8. Stick Diagrams Can also draw in shades of gray/line style. Stick Diagrams – Notations Metal 1 poly ndiff pdiff Similarly for contacts, via, tub etc..

  9. Stick Diagrams Stick Diagrams – Some rules Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

  10. Stick Diagrams Stick Diagrams – Some rules Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

  11. Stick Diagrams Stick Diagrams – Some rules Rule 3. When a poly crosses diffusion it represents a transistor. Note: If a contact is shown then it is not a transistor.

  12. Stick Diagrams Stick Diagrams – Some rules Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

  13. How to draw Stick Diagrams Stick Diagrams

  14. Stick Diagrams

  15. Stick Diagrams Power A Out C B Ground

  16. Introduction toCMOS VLSIDesignMOS devices: static and dynamic behavior

  17. Outline • DC Response • Logic Levels and Noise Margins • Transient Response • Delay Estimation

  18. DC Response • DC Response: Vout vs. Vin for a gate • Ex: Inverter • When Vin = 0 -> Vout = VDD • When Vin = VDD -> Vout = 0 • In between, Vout depends on transistor size and current • By KCL, must settle such that Idsn = |Idsp| • We could solve equations • But graphical solution gives more insight

  19. Transistor Operation • Current depends on region of transistor behavior • For what Vin and Vout are nMOS and pMOS in • Cutoff? • Linear? • Saturation?

  20. nMOS Operation

  21. nMOS Operation

  22. nMOS Operation Vgsn = Vin Vdsn = Vout

  23. nMOS Operation Vgsn = Vin Vdsn = Vout

  24. pMOS Operation

  25. pMOS Operation MOS equations

  26. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 MOS equations

  27. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0

  28. I-V Characteristics • Make pMOS is wider than nMOS such that bn = bp

  29. Current vs. Vout, Vin

  30. Load Line Analysis • For a given Vin: • Plot Idsn, Idsp vs. Vout • Vout must be where |currents| are equal in

  31. Load Line Analysis • Vin = 0 MOS equations

  32. Load Line Analysis • Vin = 0.2VDD

  33. Load Line Analysis • Vin = 0.4VDD MOS equations

  34. Load Line Analysis • Vin = 0.6VDD

  35. Load Line Analysis • Vin = 0.8VDD

  36. Load Line Analysis • Vin = VDD

  37. Load Line Summary

  38. DC Transfer Curve • Transcribe points onto Vin vs. Vout plot

  39. Operating Regions • Revisit transistor operating regions

  40. Beta Ratio • If bp / bn 1, switching point will move from VDD/2 • Called skewed gate • Other gates: collapse into equivalent inverter

  41. Noise Margins • How much noise can a gate input see before it does not recognize the input?

  42. Logic Levels • To maximize noise margins, select logic levels at

  43. Logic Levels • To maximize noise margins, select logic levels at • unity gain point of DC transfer characteristic

  44. Transient Response • DC analysis tells us Vout if Vin is constant • Transient analysis tells us Vout(t) if Vin(t) changes • Requires solving differential equations • Input is usually considered to be a step or ramp • From 0 to VDD or vice versa

  45. Inverter Step Response • Ex: find step response of inverter driving load cap

  46. Inverter Step Response • Ex: find step response of inverter driving load cap

  47. Inverter Step Response • Ex: find step response of inverter driving load cap

  48. Inverter Step Response • Ex: find step response of inverter driving load cap

  49. Inverter Step Response • Ex: find step response of inverter driving load cap

  50. Inverter Step Response • Ex: find step response of inverter driving load cap

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