SoC Design Flow & Tools: A Comprehensive Course on System-on-Chip Design Process

1. 晶片系統設計流程與工具SoC Design Flow & Tools 熊博安 (Pao-Ann Hsiung) 國立中正大學資訊工程研究所 (National Chung Cheng University, CSIE) http://www.cs.ccu.edu.tw/~pahsiung/courses/soc/ pahsiung@cs.ccu.edu.tw Class: EA-204 (05)2720411 ext. 33119 Office: EA-512

2. What will you learn from this course? • What is a System-on-Chip (SoC)? • Motivation • History • State-of-Art • What are the design issues? • Complexity: digital, analog, mixed, IP, memory, … • Hardware-software codesign • Functional Verification: full-chip, hw, sw, … • How to design and verify an SoC? • Design & Verification Flow • Design & Verification Tools

3. Who should take this course? • Interested in becoming a system (hardware-software) engineer • Interested in designing SoCs • EE background: learn system design, embedded software design, verification • CS background: learn SoC architecture, embedded hardware design, verification • Essential backgrounds: C/C++ programming, computer architecture, OS

4. Who should NOT take this course? • Only wants course credits • Only because SoC is popular • Does not like research • Does not like projects • Does not like using tools or lab work • Not creative (lack of new ideas) • Yawns and goes to sleep when someone is talking about system design

5. Reference Books (Design) • Daniel D. Gajski et al., “Specification and Design of Embedded Systems,” Prentice Hall, 1994. • Henry Chang et al., “Surviving the SoC Revolution,” Kluwer Academic Publishers, 1999. • Bassam Tabbara et al., “Function/Architecture Optimization and Co-Design of Embedded Systems,” Kluwer Academic Publishers, 2000. • Michael Keating, Pierre Bricaud, “Reuse Methodology Manual,” Kluwer Academic Publishers, 2002. • Frank Vahid, Tony Givargis, “Embedded System Design,” John Wiley & Sons, Inc., 2002. • Steve Furber, “ARM System-on-Chip Architecture,” 2nd Edition, Addison Wesley, 2000.

6. Reference Books (Verification) • Prakash Rashinkar, Peter Paterson, Leena Singh, “System-on-a-chip Verification,” Kluwer Academic Publishers, 2001. • Lionel Bening, Harry Foster, “Principles of Verifiable RTL Design,” Kluwer Academic Publishers, 2001.

7. Course Syllabus & Schedule Topic Week • Introduction 1 • System Modeling 2 ~ 4 • Hardware-Software Codesign 5 ~ 7 • Mid-Term 8 • SoC Verification 9 ~ 10 • Configurable Processors 11 • SoC Testing 12 ~ 13 • Project Presentations 14 • Final Exam 15

8. Course Grading • Mid-Term Exam 30% • Final Exam 30% • Digital Camera Project 16% • 6 Labs 24%

9. Digital Camera Project • Design a digital camera SoC with hardware and software (JPEG) • Schedule • Written Report May 31, 2005 • Presentation May 31, 2005 • Demonstration Before Final Exam • Grade: (total 16%) • Report 5%, Presentation 5%, Demo 6%

10. SIX Labs • Familiarity with Tools • Cadence SystemC/Verilog/VHDL simulators • UML Editor and Simulator • Mentor Seamless Co-Verification Environment (CVE) • FPGA design tools • Altera Quartus II v3.0, SoPC Builder • Xilinx ISE Foundation, and other tools • Coware ConvergenSC • Tensilica Xtensa Configurable Processor

11. Labs • All 6 labs (total 24%) • Assignment last ½ hour • Deadline after 2 weeks • Grading fasterhigher grades • Demonstration contact TA • TA = 邱冠綸, Ext. 23125, Lab EA305

12. SoC Design Flow & Tools ENJOY THE COURSE!!!