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The trigger-less TBit/s readout for the Mu3e experiment

The trigger-less TBit/s readout for the Mu3e experiment. Dirk Wiedner On behalf of the Mu3e collaboration. The Mu3e Signal. μ → eee rare in SM Enhanced in: Super-symmetry Grand unified models Left-right symmetric models Extended Higgs sector Large extra dimensions.

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The trigger-less TBit/s readout for the Mu3e experiment

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  1. The trigger-less TBit/s readout for the Mu3e experiment Dirk Wiedner On behalf of the Mu3e collaboration Dirk Wiedner TWEPP2013

  2. The Mu3e Signal • μ→eee rare in SM • Enhanced in: • Super-symmetry • Grand unified models • Left-right symmetric models • Extended Higgs sector • Large extra dimensions • Rare decay (BR<10-12, SINDRUM) • For BR O(10-16) • >1016 muon decays • High decay rates O(109 muon/s) Dirk Wiedner, Mu3e collaboration

  3. The Mu3e Experiment • Muon beam O(109/s) • Helium atmosphere • 1 T B-field Dirk Wiedner, Mu3e collaboration Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope

  4. The Mu3e Experiment • Muon beam O(109/s) • Helium atmosphere • 1 T B-field Dirk Wiedner, Mu3e collaboration Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope

  5. The Mu3e Experiment • Muon beam O(109/s) • Helium atmosphere • 1 T B-field Dirk Wiedner, Mu3e collaboration Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope

  6. The Mu3e Experiment • Muon beam O(109/s) • Helium atmosphere • 1 T B-field Dirk Wiedner, Mu3e collaboration Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope

  7. The Mu3e Experiment • Muon beam O(109/s) • Helium atmosphere • 1 T B-field Dirk Wiedner, Mu3e collaboration Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope

  8. Readout Requirements • 2.5 GHz muon decays • 50 ns readout frames (pixel) • O(5000) pixel chips • O(7000) scintillating fibers • O(7000) timing tiles • Online filtering Dirk Wiedner TWEPP2013

  9. Timing Detectors • Scintillating fiber hodoscope • Timing tiles • On detector zero-suppression • Poster Session: • STiC - A Mixed Mode Silicon-Photomultiplier Readout ASIC for Time-of-Flight Applications (Tobias Harion) O(7000) fibers O(7000) tiles Dirk Wiedner TWEPP2013

  10. Silicon Pixel Detector • Inner double layer • Outer double layer • Re-curl layers • Both sides (x2) • Sensor size • 1x2 cm2 inner layers • 2x2 cm2 outer layers 180 inner sensors 4680 outer sensors Dirk Wiedner TWEPP2013

  11. HV-MAPS • High Voltage Monolithic Active Pixel Sensors • HV-CMOS technology • Reversely biased ~60V • Charge collection via drift • Fast O(100 ns) • Thinning to < 50 μm possible by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876 Dirk Wiedner, Mu3e collaboration

  12. HV-MAPS • High Voltage Monolithic Active Pixel Sensors • HV-CMOS technology • Reversely biased ~60V • Charge collection via drift • Fast O(100 ns) • Thinning to < 50 μm possible by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876 Dirk Wiedner, Mu3e collaboration

  13. HV-MAPS • High Voltage Monolithic Active Pixel Sensors • HV-CMOS technology • Reversely biased ~60V • Charge collection via drift • Fast O(100 ns) • Thinning to < 50 μm possible • Integrated readout electronics • Zero suppression • 800Mbit/s serial LVDS outputs by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876 Dirk Wiedner, Mu3e collaboration

  14. HV-MAPS • High Voltage Monolithic Active Pixel Sensors • HV-CMOS technology • Reversely biased ~60V • Charge collection via drift • Fast O(100 ns) • Thinning to < 50 μm possible • Integrated readout electronics • Zero suppression • 800Mbit/s serial LVDS outputs by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876 Dirk Wiedner, Mu3e collaboration

  15. Pixel Readout Scheme Dirk Wiedner TWEPP2013

  16. Pixel Readout Scheme • Pixel logic • Pixel address (8 bit) • Frame number (4 bit) • 50 ns frames • Column logic • Pixel data • Column address • Coarse time • Frame logic • Super Frame • Contains 16 x 50 ns readout frames • + Sensor header • Readout buffer • Serializer and fast link(s) Pixel address • Fine time Pixel Logic Column address Coarse time Column Logic Frame logic Readout buffer Serializer Dirk Wiedner TWEPP2013

  17. Pixel Readout Scheme • Pixel logic • Pixel address (8 bit) • Frame number (4 bit) • 50 ns frames • Column logic • Pixel data • Column address • Coarse time • Frame logic • Super Frame • Contains 16 x 50 ns readout frames • + Sensor header • Readout buffer • Serializer and fast link(s) Pixel address Fine time 8 bit Pixel Logic 4 bit Column address 12 bit Coarse time Column Logic Frame logic Readout buffer Serializer Dirk Wiedner TWEPP2013

  18. Pixel Readout Scheme • Pixel logic • Pixel address (8 bit) • Frame number (4 bit) • 50 ns frames • Column logic • Pixel data • Column address • Coarse time • Frame logic • Super Frame • Contains 16 x 50 ns readout frames • + Sensor header • Readout buffer • Serializer and fast link(s) Pixel address • Fine time 8 bit Pixel Logic 4 bit Column address 12 bit Coarse time Column Logic 8 bit 12 bit 32 bit Frame logic Readout buffer Serializer Dirk Wiedner TWEPP2013

  19. Pixel Readout Scheme • Pixel logic • Pixel address (8 bit) • Frame number (4 bit) • 50 ns frames • Column logic • Pixel data • Column address • Coarse time • Frame logic • Contains 16 x 50 ns readout frames • + Sensor header • Super Frame • Readout buffer • Serializer and fast link(s) Pixel address • Fine time 8 bit Pixel Logic 4 bit Column address 12 bit Coarse time Column Logic 8 bit 12 bit 32 bit Frame logic Readout buffer Serializer 4 x serial @ 800 Mb/s Dirk Wiedner TWEPP2013

  20. Data Link Scheme From detector slices to time slices Dirk Wiedner TWEPP2013

  21. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Dirk Wiedner TWEPP2013

  22. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Pixel Sensor Silicon FPGAs x86 Readout board x12 PC x48 Dirk Wiedner TWEPP2013

  23. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor O(8Tbit/s) x6336 x7000 x7000 Fiber FPGAs x48 Silicon FPGAs x86 Tile FPGAs x48 Readout board x16 Readout board x8 Readout board x8 PC x48 Dirk Wiedner TWEPP2013

  24. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber FPGAs x48 Silicon FPGAs x86 Tile FPGAs x48 x376 Readout board x16 Readout board x8 Readout board x8 PC x48 Dirk Wiedner TWEPP2013

  25. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Fiber Tile Pixel Sensor Tile Fiber Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber FPGAs x48 Silicon FPGAs x86 Tile FPGAs x48 O(4Tbit/s) x376 x192 x192 Readout board x16 Readout board x8 Readout board x8 PC x48 Dirk Wiedner TWEPP2013

  26. Link Overview • Front end links • Pixel sensor to on-detector FPGA • 400 – 800 Mbit/s • LVDS • Timing detector readout • Optical links from detector • Front end FPGAs • … to readout boards • 5 Gbit/s • Optical links in counting room • Off-detector read out boards • …to PC Farm Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber FPGAs x48 Silicon FPGAs x86 Tile FPGAs x48 Readout board x16 Readout board x8 Readout board x8 x96 x96 PC x48 O(4Tbit/s) x192 Dirk Wiedner TWEPP2013

  27. Front End FPGAs • FPGAs on detector • 86 (+96) pieces • Receive sensor data • 108 LVDS inputs • 5 Gbit/s outputs • 8 optical links • … to counting house • Switching data between readout boards farms A-D Pixel Sensor 800 Mbit/s LVDS in x 108 Front end FPGA 5 Gbit/s optical Readout board A Readout board B Readout board C Readout board D Dirk Wiedner TWEPP2013

  28. Front End FPGAs • FPGAs on detector • 86 (+96) pieces • Receive sensor data • 108 LVDS inputs • 5 Gbit/s outputs • 8 optical links • … to counting house • Switching data between readout boards farms A-D Pixel Sensor 800 Mbit/s LVDS in x 108 Front end FPGA 5 Gbit/s optical Readout board A Readout board B Readout board C Readout board D Dirk Wiedner TWEPP2013

  29. Front End FPGAs • FPGAs on detector • 86 (+96) pieces • Receive sensor data • 108 LVDS inputs • 5 Gbit/s outputs • 8 optical links • … to counting house • Switching data between readout boards farms A-D Pixel Sensor 800 Mbit/s LVDS in x 108 Front end FPGA 5 Gbit/s optical Readout board A Readout board B Readout board C Readout board D Dirk Wiedner TWEPP2013

  30. Front End FPGAs • FPGAs on detector • 86 (+96) pieces • Receive sensor data • 108 LVDS inputs • 5 Gbit/s outputs • 8 optical links • … to counting house • Switching data between readout boards farms A-D Pixel Sensor 800 Mbit/s LVDS in x 108 Front end FPGA 5 Gbit/s optical Readout board A Readout board B Readout board C Readout board D Dirk Wiedner TWEPP2013

  31. Readout Board • FPGA readout boards • 4 per sub-detector • 5 Gbit/s optical inputs • 16-28 inputs • 10 Gbit/s optical output • 12 outputs to PCs • Switching network • A-D sub-farms • One output per PC Front end FPGA Front end FPGA Front end FPGA Front end FPGA 5 Gbit/s Optical x28 Sub-farm A Readout board 10 Gbit/s Optical PC PC PC x12 Dirk Wiedner TWEPP2013

  32. Readout Board • FPGA readout boards • 4 per sub-detector • 5 Gbit/s optical inputs • 16-28 inputs • 10 Gbit/s optical output • 12 outputs to PCs • Switching network • A-D sub-farms • One output per PC Front end FPGA Front end FPGA Front end FPGA Front end FPGA 5 Gbit/s Optical x28 Sub-farm A Readout board 10 Gbit/s Optical PC PC PC x12 Dirk Wiedner TWEPP2013

  33. GPU-PC Optical mezzanine connectors • PC with GPU • 10 Gbit/s Fiber input • 8 inputs from sub-detectors • Data filtering • Timing Filter on FPGA • Track filter on GPU • Data to tape < 100 MB/s FPGA PCIe board Dirk Wiedner TWEPP2013 GPU computer

  34. GPU-PC • PC with GPU • 10 Gbit/s Fiber input • 8 inputs from sub-detectors • Data filtering • Timing Filter on FPGA • Track filter on GPU • Data to tape < 100 MB/s Dirk Wiedner TWEPP2013 GPU computer

  35. GPU-PC • PC with GPU • 10 Gbit/s Fiber input • 8 inputs from sub-detectors • Data filtering • Timing Filter on FPGA • Track filter on GPU • Data to tape < 100 MB/s A B Readout board Readout board Readout board Readout board Readout board Readout board x8 10 Gbit/s Optical x8 10 Gbit/s Optical x8 PC PC Dirk Wiedner TWEPP2013

  36. Timing Filter • Entire event on PCIe FPGA • Tile and Fiber data • Easy to match • Look for three tracks • Reject data without three hits • … inside time interval 1 2 3 Dirk Wiedner TWEPP2013

  37. Timing Filter • Entire event on PCIe FPGA • Tile and Fiber data • Easy to match • Look for three tracks • Reject data without three hits • … inside time interval 1 2 3 Dirk Wiedner TWEPP2013

  38. Vertex Filter • Entire event on GPU • Large target • Large spread of muons • Easy vertex separation • Reject data without three tracks • … inside area interval on target 1 2 3 Dirk Wiedner TWEPP2013

  39. Vertex Filter • Entire event on GPU • Large target • Large spread of muons • Easy vertex separation • Reject data without three tracks • … inside area interval on target 1 2 3 Dirk Wiedner TWEPP2013

  40. Summary + + Dirk Wiedner TWEPP2013 Mu3e has 280M pixels @ >109 muons/s >1 Tbit/s data 0-suppressed serial data from active pixel sensors Switched optical network GPU filter farm with optical inputs

  41. Backup Slides Dirk Wiedner TWEPP2013

  42. Physics Motivation Standard model: • No lepton flavor violation Lepton flavor violation? Dirk Wiedner, Mu3e collaboration

  43. Physics Motivation Standard model: • No lepton flavor violation, but: • Neutrino mixing • Branching ratio <10-50 →unobservable Lepton flavor violation: μ+→e+e-e+ Dirk Wiedner, Mu3e collaboration

  44. The Mu3e Signal • μ→eee rare in SM • Enhanced in: • Super-symmetry • Grand unified models • Left-right symmetric models • Extended Higgs sector • Large extra dimensions Dirk Wiedner, Mu3e collaboration

  45. The Mu3e Background • Combinatorial background • μ+→e+νν& μ+→e+νν& e+e- • many possible combinations • Good time and • Good vertex resolution required Dirk Wiedner, Mu3e collaboration

  46. The Mu3e Background • μ+→e+e-e+νν • Missing energy (ν) • Good momentum resolution (R. M. Djilkibaev, R. V. Konoplich, Phys.Rev. D79 (2009) 073004) Dirk Wiedner, Mu3e collaboration

  47. Pixel Sensor Links • Vertex Sensor chips • 180 chips • 4 LVDS links • 800 Mbit/s per link • Central Silicon Tracker • 936 chips • 2 LVDS links • 800 Mbit/s • Recurl stations • 3744 chips • 1 LVDS link • 400 Mbit/s Dirk Wiedner TWEPP2013

  48. Pixel Sensor Links • Vertex Sensor chips • 180 chips • 4 LVDS links • 800 Mbit/s per link • Central Silicon Tracker • 936 chips • 2 LVDS links • 800 Mbit/s • Recurl stations • 3744 chips • 1 LVDS link • 400 Mbit/s Pixel Sensor 800 Mbits/s Front end FPGA Dirk Wiedner TWEPP2013

  49. Front End FPGAs • FPGAs on detector • 86 (+96) pieces • Receive sensor data • 108 LVDS inputs • 5 Gbit/s outputs • 8 optical links • … to counting house • Switching between readout boards A-D Optical transceiver FE board Dirk Wiedner TWEPP2013

  50. Average Occupancies • All numbers per frame of 50 ns • Vertex detector • 2 hits per sensor • Central silicon tracker • 0.6 hits per sensor • Recurl stations • 0.13 hit per sensor • Fiber hodoscope • 0.16 hits per fiber • Timing tiles • 0.09 hits per tile Tile occupancies Dirk Wiedner TWEPP2013

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