1 / 16

Encryption Overhead in Embedded Systems and Sensor Network Nodes: Modeling and Analysis

Encryption Overhead in Embedded Systems and Sensor Network Nodes: Modeling and Analysis. Prasanth Ganesan, Ramnath Venugopalan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller , Mihail Sichitiu Center for Embedded Systems Research

dallon
Download Presentation

Encryption Overhead in Embedded Systems and Sensor Network Nodes: Modeling and Analysis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Encryption Overhead in Embedded Systems and Sensor Network Nodes: Modeling and Analysis Prasanth Ganesan, Ramnath Venugopalan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu Center for Embedded Systems Research Departments of Computer Science / Electrical and Computer Engineering North Carolina State University

  2. Motivation • Embedded devices (8 bit processors) • Security concerns (wireless / RF) • Need for encryption (PDAs, sensor networks) • Feasible? • Too much computational overhead for low-end devices? • How about sensor networks? • Assess overhead for • Different architectures • Different encryption schemes • Derive analytical model, allows estimation for • New algorithms • New architecture

  3. Encryption Schemes

  4. Hardware Platforms

  5. Execution Times

  6. Clock Cycles

  7. Normalized Overhead for the Algorithms

  8. Code Size

  9. Performance Model – Why? • Feasibility algorithm A on platform P • derived from performance evaluation on a different platform Q • Asses encryption overhead based on architectural parameters • derive minimum requirements • New encryption schemes can be evaluated on a single hardware platform • extrapolated to other platforms

  10. Base Performance Model

  11. Multiply support: RICS vs CISC: Refinements for the ISA/architecture

  12. Model vs. Measurements for MD5

  13. Performance Model – Why? • Feasibility algorithm A on platform P • derived from performance evaluation on a different platform Q • Asses encryption overhead based on architectural parameters • derive minimum requirements • New encryption schemes can be evaluated on a single hardware platform • extrapolated to other platforms

  14. Variance of Execution (SHA-1) • Important for real-time scheduling

  15. Related Work • Brown et al.: PGP in wireless feasible (USENIX’00) • Lu et al.: RSA on smartcards costly  ~20 secs @ 3.57 MHz (SAC’00) • Perrig et al.: SPINS (MobiCom’02) • Touch: Crypto overhead on general-purpose machines (SIGCOMM’95) • Little work on embedded systems: • Freeman/Miller: M68k (MASCOTS’99) • Dai: Celeron results for Cryto++ 4.0 benchmarks

  16. Conclusion • Survey • computational requirements • for cryptographic algorithms • and embedded architectures • Experiments • mostly uniform cycle overhead for each word size (8/16/32 bits) • but differences among classes • Parameters that matter: text length, block size, architectural (few) • Uniformity  Approximate Model • Derive minimum requirements • predict performance on new hardware

More Related