1 / 33

목 차

목 차. 1. HDL 소개 및 설계방법 2 . 간단한 VHDL Modeling 2 . 디지털 변복조 방식 3. DQPSK CODING TECHNIQUES 부록 : ALTERA 설치 및 사용법. HDL 소개 및 설계방법. Why need such HDLs ?. HDL 소개 및 설계방법. The lack of a formalized description makes the task of simulation and verification difficult

damian
Download Presentation

목 차

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 목 차 • 1.HDL 소개 및 설계방법 • 2. 간단한 VHDL Modeling • 2. 디지털 변복조 방식 • 3. DQPSK CODING TECHNIQUES • 부록: ALTERA 설치 및 사용법 SungKyunKwan Univ.

  2. HDL 소개 및 설계방법 • Why need such HDLs ? SungKyunKwan Univ.

  3. HDL 소개 및 설계방법 • The lack of a formalized description makes the task of simulation and verification difficult • The lack of documentation during the design process make maintaining and re-targeting the design difficult. • Formalized input can be used for documentation, simulation, verification and synthesis (=translation+optimization+mapping) • The design description also serves as a good exchange medium between different user, as well as between user and design tools. • Readable + Modifiable + Reusable SungKyunKwan Univ.

  4. HDL 소개 및 설계방법 • Programming Language Features for HDLs • Definition + Behavior + Constraints • Definition:Data Types • format (e.g., number of bit) • Variable/Signal, Physical port • types (e.g., Boolean, integer, floating point) • data representation (e.g., signed/unsigned) • Behavior: Operators and Assignment Statements • arithmetic , Boolean , logic , bit manipulation , array access SungKyunKwan Univ.

  5. HDL 소개 및 설계방법 • Constraints on the design behavior for correct and efficient implementation • Control Constructs • if-then-else , case , loop • Execution Ordering • sequential , concurrent P1: process(clock) B1: block(clock’event AND clock=‘1’) begin begin A<= B; A <= guarded B; B<=A; B <= guarded A; end process P1; end block B1; SungKyunKwan Univ.

  6. HDL 소개 및 설계방법 • Hardware-Specific HDL Features • Interface Declarations • Port(size, mode) size (e.g., num-bit), hardware-specific feature • (e.g., Whether the port is buffered or tristate), mode (e.g., I, O, I-O) • Operators: Bit-level operator, RT-level operator • Structural Declarations • The specification of registers, counter, other H/W structures that are to be used like variables in the HDL description. SungKyunKwan Univ.

  7. HDL 소개 및 설계방법 • Design Hierarchy in VHDL: • As designs get more complex, we naturally resort to hierarchy as a means of describing, managing and capturing the complex behavior Procedural, structural, behavioral and design hierarchy SungKyunKwan Univ.

  8. HDL 소개 및 설계방법 • Interprocess CommunicationFor synchronous designs, this communication can be embedded within the process’behavioral description. In such case, the user can explicitly describe the communication using standard HDL constructs to force reads and writes on correct clock cycle. Whereas, asynchronous designs, we need protocols to achieve synchronization usingParameter passing (shared wire and memories) and Message passing (HardwareC) SungKyunKwan Univ.

  9. HDL 소개 및 설계방법 • Constraints: Constraints on the design behavior guide the synthesis of the design towards feasible realization in term of performance, cost, testability, reliability, and other physical restrictions (specifies in the declarations or on the separate files) Power 100mA Voltage 12V Technology CMOS Area 30 sq mm Freq 0 to 500MHz Clockbase clk Timing constraints: (For I=1 to 16 DO x := x * input/I; y := y + x; OD CYCLES = 3); SungKyunKwan Univ.

  10. HDL 소개 및 설계방법 • User bindings of behavioral entities to RT structures. Human designer does better than CAD in identifying critical sections. Binding of variables, operators to state, register, FU and connections. • Textual HDLs with various target applications • ISPS(‘81): instruction set processor • Sliage(‘85): high level lang. and silicon compiler for DSP • VHDL(‘88): simulation based HDL • HardwareC(‘91): synthesis of ASICs (based on C) • MIMOLA(‘85): design synthesis of several levels (pascal) SungKyunKwan Univ.

  11. HDL 소개 및 설계방법 • Graphical HDLs -- control flow • SpecChart, Gajski, ICCAD’91, StateChart, harel, ‘87: a visual formalism for complex systems Tabular HDLs • Tabular HDLs -- state-based portion • Tabular descriptions provide a concise notation for state-based design description, particularly for FSDMs (BIF: behavioral Intermediate Form, Gajski, DAC’90) • Waveform-Based HDLs • Timing diagrams graphically represent change on signals, show sequencing of events, and can also effectively show timing relationships between event (XWAVE,Birmingham,’91) SungKyunKwan Univ.

  12. HDL 소개 및 설계방법 Matching Language to Target Architecture • A user with software background Entity Full_Adder is port(X,Y : in bit; CIN : in bit; SUM : out bit; COUT: out bit); end Full_Adder; SungKyunKwan Univ.

  13. HDL 소개 및 설계방법 • A user with hardware background Architecture behave of Full_Adder is signal S1,S2,S3:bit begin S1 <= X xor Y; SUM <= S1 xor CIN after 3 ns; S2 <= X and Y; S3 <= S1 and CIN; COUT <= S2 or S3 after 5 ns; end; Synthesized H/W structure SungKyunKwan Univ.

  14. HDL 소개 및 설계방법 • Modeling Guidelines for HDLsIn order to achieve effcient hardware synthesis, we need to match the model of the language to that of the underlying target architecture. • Combinational Designs • Hardware design is composed of an interconnection of logic gates. (Boolean VHDL operators) • Functional Designs SungKyunKwan Univ.

  15. HDL 소개 및 설계방법 • Function designs are characterized by a mixture of synchronous and asynchronous behavior, in which asynchronous event may override synchronous operation. ☞ an up/down counter with asynchronous set and reset CNT_UP_CLR:block (CLR=‘1’ or (EN=‘1’ and CLK’event and CLK=‘1’)) begin CNT <= guarded B”0000” after CLRDEL when CLR=‘1’ else CNT+B”0001” after INCDEL when INC=‘1’ else CNT; end block; SungKyunKwan Univ.

  16. HDL 소개 및 설계방법 • Register-Transfer Designs • RT designs correspond to the FSMD model and have an implicit notion of states and state transitions State_Fetch: block ((CLK’event and CLK=‘1’) and (state=S0)) begin IR <= M(PC); state <= S1; end block; • Behavioral Designs (no state assigned) Design behavior is typically expressed in a sequential language style using sequential assignment statement SungKyunKwan Univ.

  17. HDL 소개 및 설계방법 • 효율적인 모델링 기법 • 대규모 설계를 위해서는 동작적 모델링. • 구현을 위해서는 합성 가능한 구문 이용 • assert, configuration, access type, file type 등은 합성불가 • Process문의 sensitivity list를 검사. • 연산 순서를 조정한 모델링 (+: 8 gates; Mux: 3 gates) SungKyunKwan Univ.

  18. HDL 소개 및 설계방법 • 연산수행을 줄이는 모델링 • 같은 연산은 한번에 수행 process(a,b,c,d) process(a,b,c,d) begin begin y1 <= a+b; y1 <= a+b; y2 <= a+b+d;  y2 <= y1+d; y3 <= a+c; y3 <= a+c; end process; end process; SungKyunKwan Univ.

  19. HDL 소개 및 설계방법 • 보다 효율적인 문장 선택 • 빠른 속도를 필요로 하는 회로에는 case문보다 if문이 효율적이다. • Simulator에 따라 다른 library와 package사용 • Library나 각package들의 이름 및 형식은 사용 하는 simulator에 따라 다를 수 있다. 예: library IEEE; use ieee.std_logic_1164.all; • 반도체 회사에서 제공하는 library를 이용한 합성 (예: 곱셈기, ROM) • 관련이 많은 부분을 그룹지어 코딩 및 합성 SungKyunKwan Univ.

  20. Library ieee;use ieee.std_logic_1164.all;entity f_adder is port(x,y,c_in : in std_logic; s_out,c_out : out std_logic);end f_adder;architecture behave of f_adder isbegin process(x,y,c_in) variable tmp : std_logic_vector(1 downto 0); Full_adder 동작적 모델링 간단한 VHDL Modeling SungKyunKwan Univ.

  21. 간단한 VHDL Modeling begin l := “00”; if x=‘1’ then l := l+1; end if ; if y=‘1’ then l := l+1; end if ; if c_in=‘1’ then l := l+1; end if ; if (l=0) or (l=2) then s_out <= ‘0’ else s_out <= ‘1’;end if; if (l=0) or (l=1) then c_out <= ‘0’ else c_out <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  22. 간단한 VHDL Modeling • Full_adder 구조적 모델링 SungKyunKwan Univ.

  23. 반가산기 모델링(Half adder)Library ieee;use ieee.std_logic_1164.all;entity h_adder is port(a,b : in std_logic; ☞ s,c : out std_logic);end h_adder;architecture behave of h_adder isbegin process(a,b) begin 간단한 VHDL Modeling if (a=b) then s <= ‘0’; else s <= ‘1’;end if; if (a=‘1’) and (b=‘1’) then c <=‘1’; else c <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  24. OR gate 모델링Library ieee;use ieee.std_logic_1164.all;entity or2 is port(a,b : in std_logic; ☞ o : out std_logic);end or2;architecture behave of or2 isbegin process(a,b) begin 간단한 VHDL Modeling if (a=‘0’) and (b=‘0’) o <=‘0’; else o <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  25. 전가산기 모델링(Full adder)Library ieee;use ieee.std_logic_1164.all;entity f_adder is port(x,y,c_in : in std_logic; ☞ s_out,c_out : out std_logic);end f_adder;architecture structural of or2 is signal st1,st2,st3 : std_logic; 간단한 VHDL Modeling component or2 port(a,b : in std_logic; o : out std_logic); end component; component h_adder port(a,b : in std_logic; s,c : out std_logic); end component; begin SungKyunKwan Univ.

  26. 간단한 VHDL Modeling HA1 : h_adder port map(x,y,st1,st2); HA2 : h_adder port map(st1,c_in,s_out,st3); ORG : or2 port map(st2,st3,c_out); end structural; SungKyunKwan Univ.

  27. 간단한 VHDL Modeling • Multiplexer 모델링 SungKyunKwan Univ.

  28. 간단한 VHDL Modeling • Entityentity Mux2X1 is port(a,b : in std_logic; sel : in std_logic; y : out std_logic);end Mux2X1; SungKyunKwan Univ.

  29. 간단한 VHDL Modeling • Architecture 1Architecture behave of Mux2X1 isbegin process(a,b,sel) begin if sel=‘0’ then y <= a; else y <= b; end if; end process;end behave; SungKyunKwan Univ.

  30. 간단한 VHDL Modeling • Architecture 2Architecture behave of Mux2X1 isbegin process(a,b,sel) begin case sel is when ‘0’ => y <= a; when others => y<=b; end case; end process;end behave; SungKyunKwan Univ.

  31. 간단한 VHDL Modeling • Architecture 3Architecture behave of Mux2X1 is signal temp : std_logic;begin process(a,b,sel) begin temp <= not(sel); y <= (a and temp) or (b and sel); end process;end behave; SungKyunKwan Univ.

  32. 간단한 VHDL Modeling • 동기10진 카운터 modeling • Library ieee;use ieee.std_logic_1164.all;entity cnt10 is port(ck,rst : in std_logic; q : buffer std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbegin SungKyunKwan Univ.

  33. 간단한 VHDL Modeling process(ck,rst) begin if ck’event and ck=‘1’ then if rst = ‘0’ then q <= “0000”; elsif q = “1001” then q<= “0000”; else q <= q+ “0001”; end if; end if; end process; end behave; SungKyunKwan Univ.

More Related