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FMCAD 2027: Will the FM Have a Real Impact on the CAD?

FMCAD 2027: Will the FM Have a Real Impact on the CAD?. Carl Pixley Disclaimer: These opinions are mine alone and not necessarily Synopsys’. Also, I tend toward hyperbole. November 6, 2007. Proposition Zero. Formal Methods ALREADY have had a major effect on CAD.

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FMCAD 2027: Will the FM Have a Real Impact on the CAD?

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  1. FMCAD 2027: Will the FM Have a Real Impact on the CAD? Carl Pixley Disclaimer: These opinions are mine alone and not necessarily Synopsys’. Also, I tend toward hyperbole. November 6, 2007

  2. Proposition Zero • Formal Methods ALREADY have had a major effect on CAD. • Most CAD tools have some form of mathematical reasoning “built in”. • Chips cannot be implemented without equivalence checking. • Constraint Based Verification is very common: It is based upon formal principles.

  3. It’s hard to make a buck in EDA. • My perspective is from the EDA industry. • For the last ~5 years the whole EDA industry has made about $5B and it really has not changed very much. • The big EDA companies have volume purchase agreements with our customers – often the deals are Texas “family style”, i.e., all you can eat for one price. • This is good for financial stability but not so good for growth and innovation.

  4. Proposition One • Automated Synthesis from algorithm (transaction) level to RTL cannot be accepted without formal HL-to-RTL equivalence. • Design managers will not accept the results of HL synthesis without a formal tool to check independently. • Simulation is well-known to not be sufficient. • It is a hard problem but we are doing it.

  5. Commentary • There are two distinct problems in C2RTL equivalence • (1) Ad hoc: one set of people construct the C models by hand and another set of people implement the C models in RTL • (2) Automated synthesis: C models made by-hand and RTL automatically derived from it. • (1) is MUCH harder than (2). • We have done both. (1) takes more effort and requires information that is hard to get sometimes (e.g., proper and complete constraints).

  6. Proposition Two • Assertion/constraint – based verification has a poor cost/benefit ratio – so far. • Caveats: • Some critical parts just have to have formal analysis to avoid disaster, e.g., bus controllers. • EDA companies now sell tools in this space and make some money from it but not a lot. • Development of methodologies and libraries of assertions help but still it is a hard sell.

  7. Proposition Three • ESL will happen because it has to. • Case in point: the cellphone • Combines RF, audio (MP3), video, full-motion video, GPS, net access, PDA, security…. • All of this has to be done with low power to conserve battery life. • Caveat: On the other hand cellphones often don’t work and aren’t life critical usually. • Time to market dictates that Cellphones must be designed (and verified) quickly.

  8. Commentary • My friend and colleague Jin Yang (Intel) believes he has found a theoretical foundation for designing a modern microprocessor (out-of-order, speculative, superscalar, etc.) in a correct-by-construction, customizable and modular manner. • This MIGHT be the effect on design in 2027 that will happen..

  9. Last year’s prediction:Synthesizable TB • Synthesizing testbenches is possible! • It looks like Eve (and probably other emulation companies) have done a lot in this direction. • Score one for me!

  10. Predictions for 2027 • The state of electronics may be so radically different from today that we may not recognize it. • By 2027 pre-formally-verified IP will be the norm for designs. • Interfaces will be much cleaner • Properties well-understood and documented • Requirements will be more mathematically expressed

  11. Predictions for 2027 • Fabrication technology (power, speed, size, etc.), cost-effectiveness and feature set will continue to distinguish chips as they do today. • Economics will continue to dominate the way electronics are designed and sold. • Fab technology will often create new problems for mathematical analysis, e.g., verification under uncertainty of parts.

  12. HL Design – Huge Research Opportunities • Model Checking at the word & transaction level • Increased capacity? • Better environmental information? • Equivalence verification to RTL • Leverage SW checking techniques • Coverage opportunities • ….

  13. Backup slides

  14. Puzzle • Fact 1: Verification accounts for 50% to 70% of the design resources (time, people, compute) on many chip projects. • Fact 2: Verification tools make only a fraction of revenue compared with implementation tools (e.g., synthesis, place and route, DFM, etc.) in EDA. • FORMAL verification tools (including logic checking) make a VERY small fraction. WHY?

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